A/D Converter. NTE2053 Datasheet

NTE2053 Converter. Datasheet pdf. Equivalent

Part NTE2053
Description Integrated Circuit 8-Bit MPU Compatible A/D Converter
Feature NTE2053 Integrated Circuit 8–Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8–b.
Manufacture NTE
Datasheet
Download NTE2053 Datasheet



NTE2053
NTE2053
Integrated Circuit
8–Bit MPU Compatible A/D Converter
Description:
The NTE2053 is a CMOS 8–bit successive approximation Analog to Digital converter in a 20–Lead DIP
type package which uses a differential potentiometric ladder – similar to the 256R products. This device
is designed to allow operation with the NSC800 and INS8080A derivative control bus, and TRI–STATER
output latches directly drive the data bus. These A/Ds appear like memory locations or I/O ports to the
microprocessor and no interfacing logic is needed.
A new differential analog voltage input allows increasing the common–mode rejection and offsetting
the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow
encoding any similar analog voltage span to the full 8 bits of resolution.
Features:
D Compatible With 8080 MPU Derivatives – No Interfacing Logic Needed – Access Time: 135ns
D Easy Interface to all Microprocessors, or Operates “Stand Alone”
D Differential Analog Voltage Inputs
D Logic Inputs and Outputs Meet Both MOS and TTL Voltage Level Specifications
D Works With 2.5V (NTE952) Voltage Reference
D On–Chip Clock Generator
D 0V to 5V Analog Input Voltage Range with Single 5V Supply
D No Zero Adjust Required
D Operates Ratiometrically or with 5V, 2.5V, or Analog Span Adjusts Voltage Reference
Absolute Maximum Ratings: (Note 1, Note 2)
Supply Voltage (Note 3), VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Voltage at Logic Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +18V
Voltage at All Other Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VCC +0.3V
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Power Dissipation (TA = +25°C), PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875mW
Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Recommended Operating Conditions: (Note 1, Note 2)
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 6.3V
Note 1. Absolute Maximum Ratings are those values beyond which the life of the device may be im-
paired.
Note 2. All voltage are measured with respect to GND, unless otherwise specified. The separate
A GND point should always be wired to the D GND.
Note 3. A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7V.



NTE2053
Electrical Characteristics: (VCC = 5V, TA = 0° to +70°C, fCLK = 640kHz unless otherwise specified)
Parameter
Test Conditions
Min Typ Max Unit
Total Unadjusted Error (Note 4)
VREF/2 = 2.500V
– – ±1/2 LSB
VREF/2 Input Resistance
2.5 8.0
k
Analog Input Voltage Range
DC CommonMode Error
V(+) or V(), Note 5
GND0.05
Over Analog Input Voltage Range
±1/16
VCC+0.05 V
±1/8 LSB
Power Supply Sensitivity
VCC = 5V ±10% Over Allowed
VIN(+) and VIN() Voltage Range,
Note 5
±1/16 ±1/8 LSB
Note 4. The NTE2053 A/D does not require a zero adjust.
Note 5. For VIN() VIN(+) the digital output code will be 0000 0000. Two onchip diodes are tied
to each analog input which will forward conduct for analog input voltages one diode drop bel-
wo GND or one diode drop greater than the VCC supply. Be careful, during testing at low VCC
levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct espe-
cially at elevated temperatures, and cause errors for analog inputs near fullscale. The spec
allows 50mV forward bias of either diode. This means that as long as the analog VIN does
not exceed the supply voltage by more than 50mV, the output code will be correct. To
achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply
voltage of 4.950V over temperature variations, initial tolerance, and loading.
AC Electrical Characteristics: (VCC = 5V, TA = +25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ
Conversion Time
TC fCLK = 640kHz, Note 7
Note 6, Note 7
103
66
Clock Frequency
Clock Duty Cycle
fCLK VCC = 5V, Note 6
Note 6
100 640
40
Conversion Rate in FreeRunning
Mode
Width of WR Input (Start Pulse Width)
Access Time (Delay from Falling Edge
of RD to Output Data Valid)
CR
tW(WR)L
tACC
INTR tied to WR with
CS = 0V, fCLK = 640kHz
CS = 0, Note 8
CL = 100pF
––
100
135
TRISTATE Control (Delay from Rising t1H, t0H CL = 10pF, RL = 10k
Edge of RD to HiZ State)
125
Delay from Falling Edge of WR or RD tWI, tRI
to Reset of INTR
300
Input Capacitance of Logic
Control Inputs
CIN
5
TRISTATE Output Capacitance
(Data Buffers)
COUT
5
Max
114
73
1460
60
8770
Unit
µs
1/fCLK
kHz
%
conv/s
ns
200 ns
200 ns
450 ns
7.5 pF
7.5 pF
Note 6. Accuracy is guaranteed at fCLK = 640kHz. At higher clock frequencies accuracy can de-
grade. For lower clock frequencies, the duty cycle limits can be extended so long as the mini-
mum clock high time interval or minimum clock low time interval is no less than 275ns.
Note 7. With an asynchronous start pulse, up to 8 clock periods may be required before the internal
clock phases are proper to start the conversion process. The start request is internally
latched.
Note 8. The CS input is assumed to bracket the WR strobe input and therefore timing is dependent
on the WR pulse width. An arbitrary wide pulse width will hold the converter on a reset mode
and the start of conversion is initiated by the low to high transition of the WR pulse.







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