NTE2102

NTE2102 Integrated Circuit NMOS, 1K Static RAM (SRAM), 350ns Description: The NTE2101 is a high–speed 1024 x 1 bit static random access read/write memory in a 16–Lead DIP type package designed using N–Channel depletion mode silicon gate technology. Static storage cells eliminate the need for clock or refresh circuitry. Low threshold silicon gate N–Channel technology allows complete DTL/TTL compatibility of all inputs and outputs as well as a single 5V supply. The separate chip enable input (CE) controlling the output allows easy memory expansion by OR–tying individual devices to a data bus. Data in and data out have the same polarity. Features: D Single 5V Supply D All Inputs and Outputs Directly DTL/TTL Compatible D Static Operation – No Clocks or Refresh D All Inputs Protected Against Static Charge D 350ns Access Time Absolute Maximum Ratings: (Note 1) Voltage at Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to +7V Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C Note 1. “Absolute Maximum Ratings” are those values beyond which the device ma...