PM7388

Preliminary PM7388 FREEDM 336A1024 Frame Engine and Datalink Manager FEATURES Single-chip multi-channel packet processor supporting line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 336 T1s, 252 E1s, or 12 DS-3s. Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure. configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle basis. Supports up to 168 multilink bundles with up to 12 member links per bundle. These bundles are composed of independent HDLC channels. Support for up to 100 ms of intra bundle skew in the receive direction when supporting the minimum. fragment size. Support for PPP header compression as per RFC 1661. Link Control protocol packets are identified by the PID as control protocols and will be forwarded to the Any-PHY interface. FRAME RELAY Link layer address lookup can be performed based on HDLC channel and 10 bit DLCI for HDLC channels supporting Frame Relay protocols. The lookup algorithm can support a maximum of 16 K connection identifiers (CIs) amongst multilink FR bundles. The connection identifiers are ignored in singlelink FR channels. Control frames are identified and forwarded to Any-PHY interface. 12 bit sequence numbers supported. FECN, BECN, and DE ingress processing as pe...