Document
05066
PSOT03LC
thru
Only One Name Means ProT ek’Tion™
PSOT36LC
UL TRA LOW CAPACIT ANCE TVS ARRA Y
APPLICA TIONS ✔ Ethernet - 10/100 Base T ✔ Cellular Phones ✔ FireWire ✔ Audio/Video Inputs ✔ Portable Electronics IEC COMPA TIBILITY (EN61000-4) ✔ 61000-4-2 (ESD): Air - 15kV, Contact - 8kV ✔ 61000-4-4 (EFT): 40A - 5/50ns ✔ 61000-4-5 (Surge): 12A, 8/20µs - Level 1(Line-Ground) & Level 2(Line-Line) FEA TURES ✔ ESD Protection > 40 kilovolts ✔ 500 Watts Peak Pulse Power per Line (tp = 8/20µs) ✔ Low Clamping Voltage ✔ Available in Multiple Voltage Types Ranging from 3V to 36V ✔ ULTRA LOW CAPACITANCE: 5pF MECHANICAL CHARACTERISTICS ✔ Molded JEDEC SOT-23 ✔ Weight 14 milligrams (Approximate) ✔ Flammability rating UL 94V-0 ✔ 8mm Tape and Reel Per EIA Standard 481 ✔ Device Marking: Marking Code SOT-23
PIN CONFIGURA TION
1 3 2
05066.R4 8/03
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PSOT03LC
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PSOT36LC
DEVICE CHARACTERISTICS MAXIMUM RATINGS @ 25°C Unless Otherwise Specified
PARAMETER Peak Pulse Power - tp= 8/20µs (See Figure 1) Operating Temperature Storage Temperature SYMBOL PPP TJ TSTG VALUE 500 -55°C to 150°C -55°C to 150°C UNITS W °C °C
ELECTRICAL CHARACTERISTICS PER LINE @ 25°C Unless Otherwise Specified
PART NUMBER (Note 1) DEVICE MARKING RATED STAND-OFF VOLTAGE MINIMUM BREAKDOWN VOLTAGE (See Note 2) @ 1mA V(BR) VOLTS 4.0 6.0 8.5 13.3 16.7 26.7 40.0 MAXIMUM CLAMPING VOLTAGE (See Fig. 2) @ IP = 1A VC VOLTS 7.0 9.8 13.4 19.0 24.0 43.0 51.0 MAXIMUM CLAMPING VOLTAGE (See Fig. 2) MAXIMUM LEAKAGE CURRENT TYPICAL CAPACITANCE
V WM VOLTS PSOT03LC PSOT05LC PSOT08LC PSOT12LC PSOT15LC PSOT24LC PSOT36LC 03L 05L 08L 12L 15L 24L 36L 3.3 5.0 8.0 12.0 15.0 24.0 36.0
@8/20µs VC @ IPP 10.9V @ 43.0A 13.5V @ 42.0A 16.9V @ 34.0A 25.9V @ 21.0A 30.0V @ 17.0A 49.0V @ 12.0A 76.8V @ 9.0A
@VWM ID µA 125 20 10 1 1 1 1
@0V, 1 MHz C pF 5 5 5 5 5 5 5
Note 1: Positive potential is applied from pin 1 to 2; pin 2 is ground. Note 2: Do not test or surge from pin 2 to 1. PIV typically greater than 100V for the rectifier diode.
FIGURE 1 PEAK PULSE POWER VS PULSE TIME
10,000
IPP - Peak Pulse Current - % of IPP PPP - Peak Pulse Current - Watts
120 100 80 60 40 20 0 tf
FIGURE 2 PULSE WAVE FORM
Peak Value IPP TEST WAVEFORM PARAMETERS tf = 8µs td = 20µs
1,000
500W, 8/20µs Waveform
e-t
100
td = t I /2 PP
10 0.01
1
10 100 td - Pulse Duration - µs
1,000
10,000
0
5
10
15 t - Time - µs
20
25
30
05066.R4 8/03
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PSOT03LC
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PSOT36LC
GRAPHS
FIGURE 3 POWER DERATING CURVE
Peak Pulse Power 8/20µs
100 80
% Of Rated Power
60
40 20 Average Power 0 0 25 50 75 100 125 TL - Lead Temperature - °C 150
FIGURE 4 OVERSHOOT & CLAMPING VOLTAGE FOR PSOT03LC
40
5 Volts per Division
30
20
10
0
ESD Test Pulse: 7 kilovolt, 1/30ns (waveform)
FIGURE 5 TYPICAL CLAMPING VOLTAGE VS PEAK PULSE CURRENT FOR PSOT05LC
16
VC - Clamping Voltage - Volts
12
8
4
0 0 2 4 6 8 10 12 IPP - Peak Pulse Current - Amps 14 16 18
05066.R4 8/03
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PSOT03LC
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PSOT36LC
APPLICA TION NOTE
The PSOTxxLC Series are low capacitance TVS arrays designed to protect I/O or data lines from the damaging effects of ESD or EFT. This product series provides unidirectional & bidirectional protection, with a surge capability of 500 Watts PPP per line for an 8/20µs waveform and ESD protection > 40 kilovolts. BIDIRECTIONAL COMMON-MODE CONFIGRUATION (Figure 1) Two PSOTxxLC devices, when used in paralell, provide protection in a common-mode configuration as depicted in Figure 1. Circuit connectivity is as follows: ✔ ✔ ✔ ✔ ✔ I/O Line is connected to Device 1, Pin 1. I/O Line is connect to Device 2, Pin 2. Device 1, Pin 2 is connected to ground. Device 2, Pin 1 is connected to ground. Device 1 & 2, Pin 3 is not connected.
Figure 1 - Common-Mode I/O Port Protection I/O LINE
1 3 2 3
2 1
BIDIRECTIONAL DIFFERENTIAL-MODE CONFIGRUATION (Figure 1) In addition, two PSOTxxLC devices, when used in paralell, provide protection in a differential-mode configuration for Ethernet applications as depicted in Figure 2. Circuit connectivity is as follows: ✔ ✔ ✔ ✔ ✔ I/O Line 1 is connected to Device 1, Pin 1. I/O Line 1 is connect to Device 2, Pin 2. I/O Line 2 is connected to Device 1, Pin 1. I/O Line 2 is connect to Device 2, Pin 2. Device 1 & 2, Pin 3 is not connected.
I/O 1
ETHERNET TRANSCEIVER
GND
Figure 2 - Differential-Mode Ethernet Protection
CIRCUIT BOARD LAYOUT RECOMMENDATIONS Circuit board layout is critical for Electromagnetic Compatibility (EMC) protection. The following guidelines are recommended: ✔ The protection device should be placed near the input terminals or connectors, the device will divert the transient current immediately before it can be coupled into the nearby traces. The path length between the TVS device and the protected line should be minimized. All conductive loops including power and ground loops should be minimized. The transient current return path to ground should be kept as short as possible to reduce parasitic inductanc.