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NTE7131 Dataheets PDF



Part Number NTE7131
Manufacturers NTE Electronics
Logo NTE Electronics
Description Integrated Circuit DC-Coupled Vertical Deflection Circuit
Datasheet NTE7131 DatasheetNTE7131 Datasheet (PDF)

NTE7131 Integrated Circuit DC–Coupled Vertical Deflection Circuit Description: The NTE7131 is an integrated circuit in a 9–Lead SIP type package designed for use in 90° and 110° color deflection systems for field frequencies of 50 to 120Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system. Features: D Few External Components D Highly Efficient Fully DC–Coupled Vertical Output Bridge Circuit D Vertical Flyback Switch D Guard Circu.

  NTE7131   NTE7131


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NTE7131 Integrated Circuit DC–Coupled Vertical Deflection Circuit Description: The NTE7131 is an integrated circuit in a 9–Lead SIP type package designed for use in 90° and 110° color deflection systems for field frequencies of 50 to 120Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system. Features: D Few External Components D Highly Efficient Fully DC–Coupled Vertical Output Bridge Circuit D Vertical Flyback Switch D Guard Circuit D Protection Against: Short–Circuit of the Output Pins (7 and 4) Short–Circuit of the Output Pins to VP D Temperature (Thermal) Protection D High EMC Immunity because of Common Mode Inputs D A Guard Signal in Zoom Mode Absolute Maximum Ratings: DC Supply Supply Voltage, VP Non–Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Flyback Supply Voltage, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V Vertical Circuit Output Current (Peak–to–Peak Value, Note 1), IO(p–p) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2A Output Voltage (Pin7), VO(A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52V Flyback Switch Peak Output Current, IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5A Thermal Data Virtual Junction Temperature, TVJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Operating Ambient Temperatrure Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25° to +75°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Thermal Resistance, Virtual Junction–to–Ambient (In Free Air), RthVJA . . . . . . . . . . . . . . . . . 40K/W Thermal Resistance, Virtual Junction–to–Case, RthVJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4K/W Short–Circuiting Time (Note 2), tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Hour Note 1. IO maximum determined by current protection. Note 2. Up to VP = 18V. Electrical Characteristics: (VP = 14.5V, TA = +25°C, VFB = 45V, fi = 50Hz, II(sb) = 400µA unless otherwise specified) Parameter DC Supply Operating Supply Voltage Flyback Supply Voltage Supply Current Vertical Circuit Output Voltage Swing (Scan) VO Idiff = 0.6mA(p–p), Vdiff = 1.8V(p–p), IO = 2A(p–p) IO = 2A(p–p), Note 3 IO = 50mA(p–p), Note 3 Output Voltage Swing (Flyback) VO(A) – VO(B) Forward Voltage of the Internal Efficiency Diode (VO(A) – VFB) Output Offset Current Offset Voltage at the Input of the Feedback Amplifier (VI(fb) – VO(B)) Output Offset Voltage as a Function of Temperature DC Output Voltage Open–Loop Voltage Gain (V7–4/V1–2) Open–Loop Voltage Gain (V7–4/V9–4, V1–2 = 0) Voltage Ratio V1–2/V9–4 Frequency Response (–3dB) Current Gain (IO/Idiff) Current Gain Drift as a Function of Temperature Signal Bias Current Flyback Supply Current Power Supply Ripple Rejection DC Input Voltage Common Mode Input Voltage Input Bias Current Common Mode Output Current Guard Circuit Output Current IO Not Active, VO(guard) = 0V Active, VO(guard) = 4.5V Output Voltage on Pin8 Allowable Voltage on Pin8 VO(guard) IO = 100µA Maximum Leakage Current = 10µA – 1.0 – – – – – – 50 2.5 5.5 40 µA mA V V VR fres GI ∆GcT II(sb) IFB PSRR VI(DC) VI(CM) Ibias IO(CM) II(sb) = 0 II(sb) = 0 ∆II(sb) = 300µA(p–p), fi = 50Hz, Idiff = 0 During Scan Note 8 Open Loop, Note 7 VO VDF |IOS| |VOS| ∆VOST VO(A) Gvo Idiff = 0.3mA, IO = 1A (M) IO = –1A (M), Idiff = 0.3mA Idiff = 0, II(sb) = 50 to 500µA Idiff = 0, II(sb) = 50 to 500µA Idiff = 0 Idiff = 0, Note 4 Note 5, Note 6 Note 5 13.2 – – V VP VFB IP No Signal, No Load 9.0 VP – 4.5 – 30 25.0 50 55 V V mA Symbol Test Conditions Min Typ Max Unit Linearity Error LE – – – – – – – – – – – – – – 50 – – – 0 – – 1 1 40 – – – – 6.5 80 80 0 40 5000 – 400 – 80 2.7 – 0.1 0.2 4 4 – 1.5 40 24 72 – – – – – – 10–4 500 100 – – 1.6 0.5 – % % V V mA mV µV/K V dB dB dB Hz K µA µA dB V V µA mA Notes: Note 3. The linearity error is measured without S–correction and based on the same measurement principle as performed on the screen. The measuring method is as follows: Divide the output signal I4 – I7 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 22 (block 10). Thus part 1 and 22 are unused. The equation for linearity error for adjacent blocks (LEAB) and not adjacent blocks (NAB) are given below L.


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