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Input/Output Port. NTE8212 Datasheet

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Input/Output Port. NTE8212 Datasheet
















NTE8212 Port. Datasheet pdf. Equivalent













Part

NTE8212

Description

Integrated Circuit Schottky / 8-Bit Input/Output Port



Feature


NTE8212 Integrated Circuit Schottky, 8 Bit Input/Output Port Description: The NTE8212 input/output port is an integr ated circuit in a 24–Lead DIP type pa ckage and consists of an 8–bit latch with three–state output buffers along with control and device selection logi c. Also included is a service request f lip–flop for the control and generati on of interrupts to the micr.
Manufacture

NTE Electronics

Datasheet
Download NTE8212 Datasheet


NTE Electronics NTE8212

NTE8212; oprocessor. Features: D Fully Parallel 8 –Bit Data Register and Buffer D Servi ce Request Flip–Flop for Interrupt Ge neration D Low Input Load Current: 0.25 mA Max D Three State Outputs D Outputs Sink 15mA D 3.65V Output High Voltge fo r Direct Interface to 8080A Processor D Asynchronous Register Clear D Replaces Buffers, Latches and Multiplexers in M icrocomputer Systems D.


NTE Electronics NTE8212

Reduces System Package Count Absolute M aximum Ratings: (TA = +25°C, Note 1 un less otherwise specified) All Output or Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0 .5V to +7V All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


NTE Electronics NTE8212

. . –1.0V to +5.5V Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA Operating Temperature R ange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C St orage Temperature Range . . . . . . . . . . . . . . . . . . ..





Part

NTE8212

Description

Integrated Circuit Schottky / 8-Bit Input/Output Port



Feature


NTE8212 Integrated Circuit Schottky, 8 Bit Input/Output Port Description: The NTE8212 input/output port is an integr ated circuit in a 24–Lead DIP type pa ckage and consists of an 8–bit latch with three–state output buffers along with control and device selection logi c. Also included is a service request f lip–flop for the control and generati on of interrupts to the micr.
Manufacture

NTE Electronics

Datasheet
Download NTE8212 Datasheet




 NTE8212
NTE8212
Integrated Circuit
Schottky, 8–Bit Input/Output Port
Description:
The NTE8212 input/output port is an integrated circuit in a 24–Lead DIP type package and consists
of an 8–bit latch with three–state output buffers along with control and device selection logic. Also
included is a service request flip–flop for the control and generation of interrupts to the microprocessor.
Features:
D Fully Parallel 8–Bit Data Register and Buffer
D Service Request Flip–Flop for Interrupt Generation
D Low Input Load Current: 0.25mA Max
D Three State Outputs
D Outputs Sink 15mA
D 3.65V Output High Voltge for Direct Interface to 8080A Processor
D Asynchronous Register Clear
D Replaces Buffers, Latches and Multiplexers in Microcomputer Systems
D Reduces System Package Count
Absolute Maximum Ratings: (TA = +25°C, Note 1 unless otherwise specified)
All Output or Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Note 1. Stress above those listed under “Absolute Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.




 NTE8212
Electrical Characteristics: (TA = 0° to +70°C, VCC = 5V ±5% unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
DC Characteristics
Input Load Current
STB, DS2, CLR, DI1 DI8 Inputs
MD Input
DS1 Input
Input Leakage Current
STB, DS, CLR, DI1 DI8 Inputs
MD Input
DS1 Input
Input Forward Voltge Clamp
Input LowVoltage
Input HighVoltage
Output LowVoltage
Output HighVoltage
Short Circuit Output Current
Output Leakage Current, High Impedance
State (DO0 DO8)
Power Supply Current
AC Characteritics
|IL1| VF = 0.45V
|IL2|
|IL3|
|IH1|
|IH2|
|IH3|
VC
VIL
VIH
VOL
VOH
IO5
IO
VR = 5.25V
IC = 5mA
IOL = 15mA
IOH = 1mA
VO = 0V, VCC = 5V
VO = 0.45V/5.25V
ICC
– – –0.25 mA
– – –0.75 mA
– – –1.0 mA
– – 10 µA
– – 30 µA
– – 40 µA
– – –1.0 V
– – 0.85 V
2.0
V
– – 0.48 V
3.65
V
15 – –75 mA
– – 20 µA
– – 130 mA
Pulse Width
Data to Output Delay
Write Enable to Output Delay
data Setup Time
Data Hold Time
Reset to Output Delay
Set to Output Delay
Output Enable/Disable Time (Note 2)
Clear to Output Delay
tpw Input Pulse Amplitude = 2.5V, 30 – – ns
tpd
Input Rise & Fall Times = 5ns,
Between 1V and 2V
30 ns
twe
Measurement made
at 1.5V with 15mA and 30pF
– – 40 ns
tset Test Load
15 – – ns
th 20 – – ns
tr – – 40 ns
ts – – 30 ns
te/td – – 45 ns
tc – – 55 ns
Note 2. R1 = 300/10K; R2 = 600/1K
Capacitance: (TA = +25°C, VCC = 5V, VBIAS = 2.5V, f = 1MHz, Note 3 unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Input Capacitance
Input Capacitance
Output Capacitance
CIN
CIN
COUT
DS1, MD
DS2, CLR, STB, DI1 DI8
DO1 DO8
– – 12 pF
– – 9 pF
– – 12 pF
Note 3. This parameter is periodically sampled and not 100% tested.




 NTE8212
Functional Description:
Data Latch
The 8 flipflops that compose the data latch are of a Dtype design. The output (Q) of the flipflop
follows the data input (D) while the clock input (C) is high. Latching occurs when the clock (C) returns
low.
The data latch is cleared by an asynchronous reset input (CLR).
(NOTE: Clock (C) overrides Reset (CLR).)
Output Buffer
The outputs of the data latch (Q) are connected to threestate, noninverting output buffers. These
buffers have a common control line (EN); enabling the buffer to transmit the data from the outputs of
the data latch (Q) or disabling the buffer, forcing the output into a high impedance state (threestate).
This highimpedance state allows the designer to connect the NTE8212 directly to the microproces-
sor bidirectional data bus.
Control Logic
The NTE8212 has four control inputs: DS1, DS2, MD and STB. These inputs are employed to control
device selection, data latching, output buffer state and the service request flipflop.
DS1, DS2 (Device Select)
These two inputs are employed for device selection. When DS1 is low and DS2 is high (DS1 DS2)
the device is selected. In the selected state the output buffer is enabled and the service request flip
flop (SR) is asynchronously set.
Service Request FlipFlop (SR)
The (SR) flipflop is employed to generate and control interrupts in microcomputer systems. It is asyn-
chronously set by the CLR input (active low). When the (SR) flipflop is set it is in the noninterrupting
state.
The output (Q) of the (SR) flipflop is connected to an inverting input of a NORgate. The other input
of the NORgate is noninverting and is connected to the device selection logic (DS1 DS2). The
output of the NORgate (INT) is active low (interrupting state) for connection to active low input prior-
ity generating circuits.
MD (Mode)
This input is employed to control the state of the output buffer and to determine the source of the clock
(C) to the data latch.
When MD is in the output mode (high) the output buffers are enabled and the source of clock (C) to
the data latch is from the device selection logic (DS1 DS2).
When MD is in the input mode (low) the output buffer state is determined by the device selection logic
(DS1 DS2) and the source of clock (C) to the data latch is the STB (Strobe) input.
STB (Strobe)
STB is employed as the clock (C) to the data latch for the input mode (MD = 0) and to synchronously
reset the service request (SR) flipflop.
Note that the SR flipflop triggers on the negative edge of STB which overrides CLR.




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