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1417G5 Dataheets PDF



Part Number 1417G5
Manufacturers Agere Systems
Logo Agere Systems
Description NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery
Datasheet 1417G5 Datasheet1417G5 Datasheet (PDF)

Data Sheet January 2000 NetLight ® 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery s s Transmitter disable input Wide dynamic range receiver with InGaAs PIN photodetector LVTTL signal-detect output Low power dissipation Raised ECL (PECL) logic data and clock interfaces Operating case temperature range: –40 °C to +85 °C Agere Systems Inc. Reliability and Qualification Program for built-in quality and reliability s s s s s Available in a small form factor, RJ-45 size, pl.

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Data Sheet January 2000 NetLight ® 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery s s Transmitter disable input Wide dynamic range receiver with InGaAs PIN photodetector LVTTL signal-detect output Low power dissipation Raised ECL (PECL) logic data and clock interfaces Operating case temperature range: –40 °C to +85 °C Agere Systems Inc. Reliability and Qualification Program for built-in quality and reliability s s s s s Available in a small form factor, RJ-45 size, plastic package, the 1417G5 and 1417H5-Type are high-performance, costeffective transceivers for ATM/SONET/SDH applications at 155 Mbits/s and 622 Mbits/s. Description The 1417G5 and 1417H5 transceivers are highspeed, cost-effective optical transceivers that are compliant with the International Telecommunication Union Telecommunication (ITU-T) G.957 specifications for use in ATM, SONET, and SDH applications. The 1417G5 operates at the OC-3/STM-1 rate of 155 Mbits/s, and the 1417H5 operates at the OC-12/ STM-4 rate of 622 Mbits/s. The transceiver features Agere Systems high-reliability optics and is packaged in a narrow-width plastic housing with an LC duplex receptacle. This receptacle fits into an RJ-45 form factor outline. The 20-pin package and pinout conform to a multisource transceiver agreement. The transmitter features differential PECL logic level data inputs and a LVTTL logic level disable input. The receiver features differential PECL logic level data and clock outputs and a LVTTL logic level signaldetect output. Features s SONET/SDH Compliant (ITU-T G.957 Specifications) — IR-1/S1.1, S4.1 Small form factor, RJ-45 size, multisourced 20-pin package Requires single 3.3 V power supply Clock recovery LC duplex receptacle Analog alarm outputs Uncooled 1300 nm laser transmitter with automatic output power control s s s s s s NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery Data Sheet January 2000 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Supply Voltage Operating Case Temperature Range Storage Case Temperature Range Lead Soldering Temperature/Time Operating Wavelength Range Symbol VCC TC Tstg — λ Min 0 –40 –40 — 1.1 Max 3.6 85 85 250/10 1.6 Unit V °C °C °C/s nm Pin Information TX 20 19 18 17 16 15 14 13 12 11 20-PIN MODULE - TOP VIEW RX 1 2 3 4 5 6 7 8 9 10 1-967(F).b Figure 1. 1417G5 and 1714H5 Transceivers, 20-Pin Configuration, Top View Table 1. Transceiver Pin Descriptions Pin Number MS Symbol Name/Description Receiver Mounting Studs. The mounting studs are provided for transceiver mechanical attachment to the circuit board. They may also provide an optional connection of the transceiver to the equipment chassis ground. Photodetector Bias. This lead supplies bias for the PIN photodetector diode. Logic Family NA MS 1 2 3 4 5 6 7 8 9 10 2 Photodetector Bias Receiver Signal Ground. VEER Receiver Signal Ground. VEER Received Recovered Clock Out. The rising edge occurs at the rising edge of CLK– the received data output. The falling edge occurs in the middle of the received data bit period. Received Recovered Clock Out. The falling edge occurs at the rising edge CLK+ of the received data output. The rising edge occurs in the middle of the received data bit period. Receiver Signal Ground. VEER Receiver Power Supply. VCCR Signal Detect. SD Normal operation: logic one output. Fault condition: logic zero output. Received DATA Out. No internal terminations will be provided. RD– Received DATA Out. No internal terminations will be provided. RD+ NA NA NA PECL PECL NA NA LVTTL PECL PECL Agere Systems Inc. Data Sheet January 2000 NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery Pin Information (continued) Table 1. Transceiver Pin Descriptions (continued) Pin Number 11 12 13 14 15 16 17 Logic Family NA NA LVTTL PECL PECL NA NA Symbol Name/Description Transmitter Transmitter Power Supply. Transmitter Signal Ground. Transmitter Disable. Transmitter Data In. Transmitter Data In Bar. Transmitter Signal Ground. Laser Diode Bias Current Monitor—Negative End. The laser bias current is accessible as a dc-voltage by measuring the voltage developed across pins 17 and 18. Laser Diode Bias Current Monitor—Positive End. See pin 17 description. Laser Diode Optical Power Monitor—Negative End. The back-facet diode monitor current is accessible as a dc-voltage by measuring the voltage developed across pins 19 and 20. Laser Diode Optical Power Monitor—Positive End. See pin 19 description. VCCT VEET TDIS TD+ TD– VEET BMON(–) 18 19 BMON(+) PMON(–) NA NA 20 PMON(+) NA Electrostatic D.


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