Document
IA82510 ASYNCHRONOUS SERIAL CONTROLLER FEATURES
• • • • • • Form, Fit, and Function Compatible with the Intel® 82510
Data Sheet
As of Production Ver. 01
Packaging options available: 28 Pin Plastic or Ceramic DIP, 28 Pin Plastic Leaded Chip Carrier, 28 Pin Ceramic Leadless Chip Carrier Asynchronous Serial Channel Operation Separate Transmit and Receive FIFOs with Programmable Threshold Programmable Baud Rate Generators up to 288K Baud Special Protocol Features - Control Character Recognition - Auto Echo and Loopback Modes - 9-Bit Protocol Support - 5 to 9 Bit Character Format
The IA82510 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces replacement ICs using its MILESTM , or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA82510 including functional and I/O descriptions, electrical characteristics, and applicable timing.
Package Pinout
IA82510
D4 D5 D6 D7 INT TXD VSS X2 or OUT2n X1 or CLK SCLK or RIn DSRn or TA or OUT0n DCDn or ICLK or OUT1n RXD CTSn (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (28) D3 D2 D1 D0 A2 A1 A0 VDD RDn WRn CSn RESET RTSn DTRn or TB INT TXD VSS X2 or OUT2n X1 or CLK SCLK or RIn DSRn or TA or OUT0n (5) (6) (7) (8) (9) (10) (11)
D7 D6 D5 D4 D3 D2 D1
28 Pin DIP
(27) (26) (25) (24) (23) (22) (21) (20) (19) (18) (17) (16) (15)
(4)
(3) (2) (1) (28) (27) (26) (25) (24) D0 A2 A1 A0 VDD RDn WRn
IA82510 28 Pin LCC
(23) (22) (21) (20) (19)
(12) (13) (14) (15) (16) (17) (18)
DCDn or ICLK or OUT1n
DTRn or TB
Copyright © 2001
ENG211001219-01 The End of Obsolescence™
RESET
RXD
CTSn
RTSn
CSn
innovASIC
www.innovasic.com Customer Support: 1-888-824-4184
Page 1 of 14
IA82510 ASYNCHRONOUS SERIAL CONTROLLER DESCRIPTION
Data Sheet
As of Production Ver. 01
The IA82510 is an asynchronous serial controller that provides a CPU interface to one transmit and one receive channel. It is Form, Fit, and Function compatible with the Intel 82510. Configuration registers are used to control the serial channel, interrupts, and modes of operation. The CPU controls this device via address and data lines with read/write control. The CPU also uses this interface to read and write data to receive and transmit data through the serial channel. FIFOs and various serial modes can be used to help off-load the CPU from transmitting and receiving data. An interrupt line provides an indication to the CPU that the device requires servicing. The device can be configured for 8250A/16450 compatibility.
Functional Block Diagram
IA82510
A(2:0) D(7:0) RDn WRn CSn INT RESET RECEIVER RXD CTSn RTSn TIMING (Baud Rate Generators A & B, Clocking PIN CONFIGURATION DSRn or TA or OUT0n DCDn or ICLK or OUT1n DTRn or TB MODEM BUS INTERFACE (Reset Logic, Registers, Interrupt Generation, TRANSMITTER
TXD
CONFIG., STATUS, RXDATA TXDATA
X1 or CLK X2 or OUT2n SCLK or RIn
Copyright © 2001
ENG211001219-01 The End of Obsolescence™
innovASIC
www.innovasic.com Customer Support: 1-888-824-4184
Page 2 of 14
IA82510 ASYNCHRONOUS SERIAL CONTROLLER
Functional Overview
Transmitter
Data Sheet
As of Production Ver. 01
The Transmit function consists of a 4 × 11 bit FIFO, and a Transmit Engine. The 4 × 11 FIFO is configurable as any depth between one and four words inclusive. The transmit engine is responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin. The transmit engine is highly configurable to be compatible with numerous formats, including 16450 and 8250 modes of communication. Transmit Communication parameters that can be programmed include: • Parity modes • Stop Bits • Character Length • FIFO Depth • Clocking Options • RTS and CTS modes See the Register Description for more details. Receiver The Receiver function consists of a 4 × 11 configurable FIFO and a Receive Engine. The receive engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing the data in the FIFO. The receive engine is highly configurable with parameters that include: • Parity modes • Stop Bits • Character Length • FIFO Depth • Clocking Options • Address Matching Options • Control Character Detection • RTS and CTS modes See the Register Description for more details. Bus Interface The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read and write the IA82510 Registers. It consists of the following I/O lines: • A0, A1, A2 : 3 Bit Address • D0-D7 : 8 Bit Data • RDn: Active Low Read Enable • WRn: Active Low Write Enable • CSn: Active Low Chip Select • INT: Interrupt Ou.