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RSECL* Outputs. NBSG11MNR2 Datasheet

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RSECL* Outputs. NBSG11MNR2 Datasheet
















NBSG11MNR2 Outputs. Datasheet pdf. Equivalent













Part

NBSG11MNR2

Description

2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs



Feature


NBSG11 2.5V/3.3V SiGe 1:2 Differential C lock Driver with RSECL* Outputs *Reduce d Swing ECL http://onsemi.com The NBSG 11 is a 1-to-2 differential fanout buff er, optimized for low skew and ultra-lo w JITTER. Inputs incorporate internal 5 0 W termination resistors and accept NE CL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Outputs a re RSECL (Reduced .
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Datasheet
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ON NBSG11MNR2

NBSG11MNR2; Swing ECL), 400 mV. MARKING DIAGRAM* SG 11 LYW • • • • • • • M aximum Input Clock Frequency up to 12 G Hz Typical Maximum Input Data Rate up t o 12 Gb/s Typical 30 ps Typical Rise an d Fall Times 125 ps Typical Propagation Delay RSPECL Output with Operating Ran ge: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC.


ON NBSG11MNR2

= 0 V with VEE = -2.375 V to -3.465 V R SECL Output Level (400 mV Peak-to-Peak Output), Differential Output Only 50 W Internal Input Termination Resistors F CBGA-16 BA SUFFIX CASE 489 QFN-16 MN S UFFIX CASE 485G SG11 ALYW • • Com patible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices A = Assembly Loc ation L = Wafer Lot Y = Year W = Work W eek *For further detai.


ON NBSG11MNR2

ls, refer to Application Note AND8002/D ORDERING INFORMATION Device NBSG11BA N BSG11BAR2 Package 4x4 mm FCBGA-16 4x4 m m FCBGA-16 3x3 mm QFN-16 3x3 mm QFN-16 Shipping 100 Units / Tray 500 / Tape & Reel NBSG11MN NBSG11MNR2 123 Units / Rail 3000 / Tape & Reel Board NBSG11BA EVB Description NBSG11BA Evaluation Bo ard © Semiconductor Components Indust ries, LLC, 2003 1 .





Part

NBSG11MNR2

Description

2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs



Feature


NBSG11 2.5V/3.3V SiGe 1:2 Differential C lock Driver with RSECL* Outputs *Reduce d Swing ECL http://onsemi.com The NBSG 11 is a 1-to-2 differential fanout buff er, optimized for low skew and ultra-lo w JITTER. Inputs incorporate internal 5 0 W termination resistors and accept NE CL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Outputs a re RSECL (Reduced .
Manufacture

ON

Datasheet
Download NBSG11MNR2 Datasheet




 NBSG11MNR2
NBSG11
2.5V/3.3V SiGe 1:2
Differential Clock Driver
with RSECL* Outputs
*Reduced Swing ECL
The NBSG11 is a 1-to-2 differential fanout buffer, optimized for
low skew and ultra-low JITTER.
Inputs incorporate internal 50 W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS,
LVTTL, or LVDS. Outputs are RSECL (Reduced Swing ECL),
400 mV.
Maximum Input Clock Frequency up to 12 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
30 ps Typical Rise and Fall Times
125 ps Typical Propagation Delay
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
RSECL Output Level (400 mV Peak-to-Peak Output), Differential
Output Only
50 W Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
http://onsemi.com
MARKING
DIAGRAM*
FCBGA-16
BA SUFFIX
CASE 489
SG
11
LYW
QFN-16
MN SUFFIX
CASE 485G
SG11
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For further details, refer to Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
NBSG11BA
NBSG11BAR2
4x4 mm
FCBGA-16
4x4 mm
FCBGA-16
100 Units / Tray
500 / Tape & Reel
NBSG11MN
NBSG11MNR2
3x3 mm
QFN-16
3x3 mm
QFN-16
123 Units / Rail
3000 / Tape & Reel
Board
NBSG11BAEVB
Description
NBSG11BA Evaluation Board
© Semiconductor Components Industries, LLC, 2003
April, 2003 - Rev. 6
1
Publication Order Number:
NBSG11/D




 NBSG11MNR2
1 2 34
A VTCLK
NC
NC Q1
B CLK VEE VCC Q1
C CLK VEE VCC Q0
D VTCLK
NC
NC Q0
Figure 1. BGA-16 Pinout (Top View)
NBSG11
VEE NC NC VCC
16 15 14 13
Exposed Pad (EP)
VTCLK 1
CLK 2
CLK 3
VTCLK 4
NBSG11
12 Q0
11 Q0
10 Q1
9 Q1
5678
VEE NC NC VCC
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
Description
D1 1 VTCLK
-
Internal 50 W Termination Pin. See Table 2.
C1
2
CLK
ECL, CML,
Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.
LVCMOS, LVDS,
LVTTL Input
B1
3
CLK
ECL, CML,
Noninverted Differential Input. Internal 75 kW to VEE.
LVCMOS, LVDS,
LVTTL Input
A1 4 VTCLK
-
Internal 50 W Termination Pin. See Table 2.
B2,C2
A2,A3,D2,
D3
5,16
6,7,14,15
VEE
NC
- Negative Supply Voltage
- No Connect
B3,C3
A4
B4
C4
D4
N/A
8,13
VCC
- Positive Supply Voltage
9
Q1
RSECL Output
Inverted Differential Output 1. Typically Terminated with 50 W to
VTT = VCC - 2 V
10
Q1
RSECL Output
Noninverted Differential Output 1. Typically Terminated with 50 W to
VTT = VCC - 2 V
11
Q0
RSECL Output
Inverted Differential output 0. Typically Terminated with 50 W to
VTT = VCC - 2 V
12
Q0
RSECL Output
Noninverted Differential Output 0. Typically Terminated with 50 W to
VTT = VCC - 2 V
- EP
- Exposed Pad (Note 2)
1. The NC pins are electrically connected to the die and must be left open.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat-sinking conduit.
3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and
if no signal is applied then the device will be susceptible to self-oscillation.
http://onsemi.com
2




 NBSG11MNR2
NBSG11
VTCLK
50 W
CLK
CLK
VCC
36.5 KW
50 W 75 KW
75 KW
VTCLK
VEE
Figure 3. Logic Diagram
Q1
Q1
Q0
Q0
Table 2. Interfacing Options
INTERFACING OPTIONS
CML
LVDS
AC-COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
CONNECTIONS
Connect VTCLK and VTCLK to VCC
Connect VTCLK and VTCLK together
Bias VTCLK and VTCLK Inputs within
(VIHCMR) Common Mode Range
Standard ECL Termination Techniques
An external voltage should be be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and VCC/2
for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor (CLK, CLK)
Internal Input Pullup Resistor (CLK)
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity (Note 4)
FCBGA-16
QFN-16
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional information, see Application Note AND8003/D.
Value
75 kW
36.5 kW
> 2 kV
> 100 V
Level 3
Level 1
UL 94 V-0 @ 0.125 in
125
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3




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