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Receiver/Driver/Translator Buffer. NBSG16MMN Datasheet

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Receiver/Driver/Translator Buffer. NBSG16MMN Datasheet
















NBSG16MMN Buffer. Datasheet pdf. Equivalent













Part

NBSG16MMN

Description

2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer



Feature


NBSG16M 2.5V/3.3V Multilevel Input to CM L Clock/Data Receiver/Driver/Translator Buffer The NBSG16M is a differential c urrent mode logic (CML) receiver/driver /translator buffer. The device is funct ionally equivalent to the EP16, LVEP16, or SG16 devices with CML output struct ure and lower EMI capabilities. Inputs incorporate internal 50 W termination r esistors and accep.
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Datasheet
Download NBSG16MMN Datasheet


ON NBSG16MMN

NBSG16MMN; t LVNECL (Negative ECL), LVPECL (Positiv e ECL), LVTTL, LVCMOS, CML, or LVDS. Th e CML output structure contains interna l 50 W source termination resistor to V CC. The device generates 400 mV output amplitude with 50 W receiver resistor t o VCC. The VBB pin is internally genera ted voltage supply available to this de vice only. For all single−ended input conditions, the unu.


ON NBSG16MMN

sed complementary differential input is connected to VBB as a switching referen ce voltage. VBB may also rebias AC coup led inputs. When used, decouple VBB via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open. http://onsemi.com MARKING DIAGRAM* QFN 16 MN SUFFIX CASE 485G A L Y W SG 16M ALYW = Assembly Lo.


ON NBSG16MMN

cation = Wafer Lot = Year = Work Week * For additional marking information, ref er to Application Note AND8002/D. • Maximum Input Clock Frequency > 10 GHz Typical • • • • • • Maximum Input Data Rate > 10 Gb/s Typical 120 ps Typical Propagation Delay 35 ps Typi cal Rise and Fall Times Positive CML Ou tput with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Nega.





Part

NBSG16MMN

Description

2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer



Feature


NBSG16M 2.5V/3.3V Multilevel Input to CM L Clock/Data Receiver/Driver/Translator Buffer The NBSG16M is a differential c urrent mode logic (CML) receiver/driver /translator buffer. The device is funct ionally equivalent to the EP16, LVEP16, or SG16 devices with CML output struct ure and lower EMI capabilities. Inputs incorporate internal 50 W termination r esistors and accep.
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Datasheet
Download NBSG16MMN Datasheet




 NBSG16MMN
NBSG16M
2.5V/3.3V Multilevel Input
to CML Clock/Data
Receiver/Driver/Translator
Buffer
The NBSG16M is a differential current mode logic (CML)
receiver/driver/translator buffer. The device is functionally equivalent
to the EP16, LVEP16, or SG16 devices with CML output structure and
lower EMI capabilities.
Inputs incorporate internal 50 W termination resistors and accept
LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL,
LVCMOS, CML, or LVDS. The CML output structure contains
internal 50 W source termination resistor to VCC. The device
generates 400 mV output amplitude with 50 W receiver resistor to
VCC.
The VBB pin is internally generated voltage supply available to this
device only. For all single−ended input conditions, the unused
complementary differential input is connected to VBB as a switching
reference voltage. VBB may also rebias AC coupled inputs. When
used, decouple VBB via a 0.01 mF capacitor and limit current sourcing
or sinking to 0.5 mA. When not used, VBB output should be left open.
Maximum Input Clock Frequency > 10 GHz Typical
Maximum Input Data Rate > 10 Gb/s Typical
120 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Positive CML Output with Operating Range: VCC = 2.375 V to
3.465 V with VEE = 0 V
Negative CML Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
CML Output Level; 400 mV Peak−to−Peak Output with
50 W Receiver Resistor to VCC
50 W Internal Input and Output Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL
and SG Devices
VBB Reference Voltage Output
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MARKING
DIAGRAM*
QFN−16
MN SUFFIX
CASE 485G
SG
16M
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping
NBSG16MMN
3x3 mm
QFN−16
123 Units / Rail
NBSG16MMNR2
3x3 mm 3000/Tape & Reel
QFN−16
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
April, 2004 − Rev. 3
1
Publication Order Number:
NBSG16M/D




 NBSG16MMN
NBSG16M
VCC VBB VEE VEE
16 15 14 13
Exposed Pad (EP)
VTD 1
D2
D3
VTD 4
NBSG16M
12 VCC
11 Q
10 Q
9 VCC
5678
VCC NC VEE VEE
Figure 1. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1 VTD
Description
Internal 50 W Termination Pin. See Table 2. (Note 3)
2 D LVDS, CML, ECL, LVTTL, Inverted Differential Input (Note 3)
LVCMOS Input
3 D LVDS, CML, ECL, LVTTL, Noninverted Differential Input. (Note 3)
LVCMOS Input
4 VTD
5 VCC
− Internal 50 W Termination Pin. See Table 2. (Note 3)
− Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guar-
antee proper operation.
6 NC
− No Connect (Note 1)
7 VEE
− Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guar-
antee proper operation.
8 VEE
− Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guar-
antee proper operation.
9 VCC
− Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guar-
antee proper operation.
10 Q
CML Output
Noninverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2)
11 Q
CML Output
Inverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2)
12 VCC
− Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guar-
antee proper operation.
13 VEE
− Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guar-
antee proper operation.
14 VEE
− Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guar-
antee proper operation.
15 VBB
16 VCC
− Internally Generated ECL Reference Output Voltage
− Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guar-
antee proper operation.
− EP
− Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must
be attached to a heat−sinking conduit.
1. The NC pins are electrically connected to the die and MUST be left open.
2. CML outputs require 50 W receiver termination resistor to VCC for proper operation.
3. In the differential configuration when the input termination pin (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self−oscillation.
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2




 NBSG16MMN
VCC
VTD
50 W 50 W
D
D
VTD
50 W
50 W
VEE
Figure 2. Logic Diagram
NBSG16M
VCC
50 W
Q
Q
50 W
VBB
16 mA
VEE
Figure 3. CML Output Structure
Table 2. Interfacing Options
INTERFACING OPTIONS
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
CONNECTIONS
Connect VTD and VTD to VCC
Connect VTD and VTD together
Bias VTD and VTD Inputs within (VIHCMR)
Common Mode Range
Standard ECL Termination Techniques
An external voltage should be applied to the
unused complimentary differential input.
Nominal voltage 1.5 V for LVTTL and VCC/2 for
LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1 kV
> 100 V
> 4 kV
Moisture Sensitivity (Note 4)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
145
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Q
Q
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