N-Channel Logic Level Enhancement Mode Field Effect Transistor
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast
switching, and low in-line power loss are needed in a very
small outline surface mount package.
1.3 A, 20 V. RDS(ON) = 0.21 Ω @ VGS= 2.7 V
RDS(ON) = 0.16 Ω @ VGS= 4.5 V.
Industry standard outline SOT-23 surface mount package
using poprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
Absolute Maximum Ratings
TA = 25°C unless otherwise noted
Gate-Source Voltage - Continuous
ID Maximum Drain Current - Continuous
PD Maximum Power Dissipation
TJ,TSTG Operating and Storage Temperature Range
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
-55 to 150
© 1997 Fairchild Semiconductor Corporation