June 1997
NDS336P P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOTTM-3 P-Cha...
June 1997
NDS336P P-Channel Logic Level Enhancement Mode Field Effect
Transistor
General Description
SuperSOTTM-3 P-Channel logic level enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
Features
-1.2 A, -20 V, RDS(ON) = 0.27 Ω @ VGS= -2.7 V RDS(ON) = 0.2 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.0V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface package. Mount
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Absolute Maximum Ratings
Symbol VDSS VGSS ID PD TJ,TSTG Parameter Drain-Source Voltage
T A = 25°C unless otherwise noted
NDS336P -20 ±8
(Note 1a)
Units V V A
Gate-Source Voltage - Continuous Maximum Drain Current - Continuous - Pulsed Maximum Power Dissipation
(Note 1a) (Note 1b)
-1.2 -10 0.5 0.46 -55 to 150
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