Document
February 1997
NDS9410S Single N-Channel Enhancement Mode Field Effect Transistor
General Description
SO-8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
Features
7.0 A, 30 V. RDS(ON) = 0.03 Ω @ VGS = 10 V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package.
____________________________________________________________________________________________
5 6 7 8
4 3 2 1
ABSOLUTE MAXIMUM RATINGS T A = 25°C unless otherwise noted
Symbol VDSS VGSS ID PD Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Maximum Power Dissipation
(Note 1a) (Note 1b) (Note 1c) (Note 1a)
NDS9410S 30 ±20 7 25 2.5 1.2 1 -55 to 150
Units V V A W
TJ,TSTG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)
50 25
°C/W °C/W
© 1997 Fairchild Semiconductor Corporation
NDS9410S Rev.B
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 24 V, VGS = 0 V TJ= 55°C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse Gate Threshold Voltage Static Drain-Source On-Resistance On-State Drain Current Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 10 V, ID = 7 A, VGS = 10 V VDD = 10 V, ID = 1 A, VGEN = 10 V, RGEN = 6 Ω VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = 250 µA TJ= 125°C VGS = 10 V, ID = 7 A TJ= 125°C VGS = 10 V, VDS = 5 V VDS = 10 V, ID = 7 A VDS = 15 V, VGS = 0 V, f = 1.0 MHz 25 11 670 490 150 10 15 19 12 18 4 6 20 30 40 25 25 S pF pF pF ns ns ns ns nC nC nC 2 1.4 2.2 1.6 0.026 0.036 30 1 10 100 -100 4 2.8 0.03 0.055 V µA µA nA nA V
ON CHARACTERISTICS (Note 2)
Ω
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS (Note 2)
NDS9410S Rev.B
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol IS VSD
Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design w.