Document
NWK914D
NWK914D
PHY/PMD High Speed Copper Media Transceiver Preliminary Information
DS4829 - 1.1 December 1997
The NWK914D is a Physical Layer device designed for use in 100BASE-TX applications. The NWK914D has integrated the 100mb/s transceiver, clock and data recovery and NRZI conversion circuitry. It is designed for use in cost effective NIC adapter cards and 100BASE-TX repeater and switch applications. The device connects through a 5 bit symbol interface directly with any MAC controller that includes the PCS layer, resulting in a simple and cost effective solution. It will also interface with a PCS device such as the NWK935 to form a complete 100BASE-TX Physical Layer for connection to the IEEE 802.3 standard MII interface.
RDAT4 RDAT3 RDAT2 RDAT1 RDAT0 TXC TTLVCC REFCLK TDAT0 TDAT1 TDAT2 TDAT3
52 51 50 49 48 47 46 45 44 43 42 41 40
TDAT4
TTLGND N/C N/C RXC SDT RDLV CC N/C N/C RXPLLGND LFRB LFRA RXPLLV CC RXVCC
FEATURES s Compatible with IEEE-802.3 Standards s Operates over 100 Meters of STP and Category 5 UTP cable s Five Bit TTL Level Symbol Interface s Integrated Clock and Data Recovery s Supports Full-duplex Operation s Integral 10 Mb/s Buffer for Dual 10 Mb/s & 100 Mb/s Applications s Adaptive Equalization s 25MHz to 125MHz Transmit Clock Multiplier s Programmable TX Output Current s Base Line Wander Correction
1 2 3 4 5 6 7 8 9 10 11 12 13
39 38 37 36 35 34 33 32 31 30 29 28 27
TTLGND TEST TESTIP N10/100 LBEN TDLV CC TXOE TXPLLV CC LFTA LFTB TXPLLGND BGAPGND SUBGND
RXGND RXIP RXIN RXVCC 1 EQSEL 10TXIN 10TXIP TXVCC TXON TXOP TXGND TXREF BGAPVCC
14 15 16 17 18 19 20 21 22 23 24 25 26
GP52
Fig.1 Pin connections - top view
s Single +5V supply s 52 Pin PQFP package ORDERING INFORMATION NWK914D/CG/GP1N
MAC or Repeater Controller IC
MII Interface
Symbol Interface
NWK935 100 PCS
NWK914D
Isolation Magnetics
RJ-45
Fig.2 Simplified system diagram
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NWK914D
ABSOLUTE MAXIMUM RATINGS
Operation at absolute maximum ratings is not implied. Exposure to stresses outside those listed could cause permanent damage to the device. DC Supply voltage (VCC) Storage temperature (tst) ESD -0.5 to +7V -65 to +150° C 2kV HBM
RECOMMENDED OPERATING CONDITIONS
DC supply voltages (VCC) +5V ± 5% Operating temperature (TA) 0°C to +70°C (+25°C typ.) 750mW (typ.) Power dissipation (P D)
ELECTRICAL CHARACTERISTICS
Recommended operating conditions apply except where stated. Characteristic DC characteristics Total VCC supply current TTL high level I/P voltage TTL low level I/P voltage TTL high level I/P current TTL low level I/P current EQSEL high level I/P voltage EQSEL low level I/P voltage EQSEL floating level I/P EQSEL high level I/P current EQSEL low level I/P current TTL high level O/P voltage TTL low level O/P voltage TTL high level O/P current TTL low level O/P current Transmit O/P current pins TXOP, TXON Differential RX I/P signal voltage RX I/P common mode voltage RX I/P impedance Signal detect threshold Low voltage shutdown PLL characteristics 3dB bandwidth Damping factor Peaking Overshoot Static error Jitter VCO characteristics Centre frequency Deviation Gain @125MHz ±40 70 125 MHz MHz/V MHz 50 2 ±0.5 .005 5 0.5 dB % ns ns kHz VTH ICC VIH VIL IIH IIL VIH VIL VIZ IIH IIL VOH VOL IOH IOL 2 4.2 2.4 150 VCC/2 40 1.4 VCC/2 50 3.8 0.8 20 –400 0.8 1400 –1400 0.5 –200 4 24 mA V V µA µA V V V µA µA V V µA mA mA Vp-p V % V RREF = 1300Ω 100Mb/s data measured on device pins 100Mb/s data, 0mCable RX I/Ps floating kΩ wrt normalized output of equalizer VIH = VCC VIL = 0V IOH = 20µA IOL = 4mA device only VIH = VCC VIL = 0.4V Symbol Min. Value Typ. Max. Units Conditions
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NWK914D
TTLVCC
LFTA
LFTB
RXPLLVCC TXPLLVCC
TXOE
TXREF
10TXIN
10TX IP
TDLVCC
N10/100
RDLVCC
REFCLK TXC TDAT0 TDAT1 TDA T2 TDAT3 TDAT4 BGAPVCC BGAPGND RXC RDAT0 RDAT1 RDAT2 RDAT3 RDA T4
TIMES FIVE CLOCK MULTIPLIER
125 MHz
LOW VOLTAGE SHUT DOWN
CURRENT REFERENCE 10 Mb/s
TXVCC
SHIFTER & NRZ to NRZI
B AND GAP VOLTAGE REFERENCE
NRZI to MLT-3
100 Mb/s
TXOP TXON TXGND
DIVIDE CLOCK by FIVE
CLOCK RECOVERY PLL,125MHZ
TTL 3 LEVEL
LBEN
SHIFTER & NRZI to NRZ
COMPARATORS MLT-3 to NRZI
ADAPTIVE EQUALIZER
EQSEL RXIP RXIN RXVCC 2
TTL
SIGNAL DETECT
RXV CC1 RXGND SUBGND
TTLGND1 TTLGND2
LFRA
LFRB
SDT
RXPLLGND TXPLLGND TESTIP
TEST
Fig.3 System block diagram
FUNCTIONAL DESCRIPTION
The functional blocks within the device are shown in Fig. 3. These are described below:NRZ to MLT3 Encoder The serial data from the shifter then passes through an encoder which converts the NRZI binary data into the three level MLT-3 format for transmission by the 'TXO' outputs. Transmit Line Drivers There are two on-chip Line Drivers both of which share the output pins TXOP and TXON. The N10/100 pin is used to control which driver is active and allowed to drive the line. When held high the MLT-3 data is output by the 100Mb/s driver. This driver consists of differential current source outputs with programmable sink capability, designed to drive a nominal.