Document
INTEGRATED CIRCUITS
DATA SHEET
OQ2541HP; OQ2541U SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE
Product specification Supersedes data of 1999 Mar 19 File under Integrated Circuits, IC19 1999 May 27
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE
FEATURES • Data and clock recovery up to 2.5 Gbits/s • Multirate configurable (155, 622, 1250 or 2500 Mbits/s) • Differential data input with 2.5 mV (p-p) typical sensitivity • Differential Current-Mode Logic (CML) data and clock outputs with 50 Ω driving capability • Adjustable CML output level • Loop mode for system testing • Bit error rate related loss of signal detection • Few external components needed • Single supply voltage • Power dissipation 350 mW (typical value) • LQFP48 plastic package. ORDERING INFORMATION TYPE NUMBER OQ2541HP OQ2541U PACKAGE NAME LQFP48 − DESCRIPTION APPLICATIONS
OQ2541HP; OQ2541U
• Data and clock recovery in STM1/OC3, STM4/OC12 and STM16/OC48 transmission systems • Data and clock recovery in Gigabit Ethernet (GE) transmission systems. DESCRIPTION The OQ2541 is a data and clock recovery IC intended for use in Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) systems. The circuit recovers data and extracts the clock signal from an incoming bitstream up to 2.5 Gbits/s. It can be configured for use in STM1/OC3, STM4/OC12, STM16/OC48 and Gigabit Ethernet systems.
VERSION SOT313-2 −
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm bare die; 2360 × 2360 × 380 µm
1999 May 27
2
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE
BLOCK DIAGRAM
OQ2541HP; OQ2541U
handbook, full pagewidth
LOS 39
DOUT622 DOUT1250 DOUT155 27 28 30
AREF 48
ENL 1
FREQUENCY DIVIDER 1 1/2/4/16
42 43 45 DATA AND CLOCK OUTPUT 46 6 7 3 4
DOUT DOUTQ COUT COUTQ DLOOP DLOOPQ CLOOP CLOOPQ
33 DIN 34 DINQ ALEXANDER PHASE DETECTOR
OQ2541
enable 21 22 FREQUENCY WINDOW DETECTOR (1000 ppm)
CREF CREFQ
+
∫ dt
130 pF
proportional path
VCRO 2.5 GHz
integrating path
130 pF POWER CONTROL 37
i.c.
5
13, 18, 19, 36, 40 FREQUENCY DIVIDER 2 64/128 12 LOCK 9 DREF19 24 16 15
PC
17
2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47
25 VEE1
31
MBH972
GND
DREF39 CAPDOQ CAPUPQ
VEE2
Fig.1 Block diagram.
1999 May 27
3
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE
PINNING SYMBOL ENL GND CLOOP CLOOPQ GND DLOOP DLOOPQ GND DREF19 GND GND LOCK i.c. GND CAPUPQ CAPDOQ GND i.c. i.c. GND CREF CREFQ GND DREF39 VEE1 GND DOUT1250 DOUT622 GND DOUT155 VEE2 GND DIN DINQ GND i.c. PC GND LOS i.c. 1999 May 27 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 loop mode enable input (active LOW) ground; note 1 clock output in loop mode (differential) inverted clock output in loop mode (differential) ground; note 1 data output in loop mode (differential) inverted data output in loop mode (differential) ground; note 1 reference frequency select input 1 (see Table 2) ground; note 1 ground; note 1 phase lock detection output internally connected; note 2 ground; note 1 external loop filter capacitor connection external loop filter capacitor return connection ground; note 1 internally connected; note 2 internally connected; note 2 ground; note 1 reference clock input (differential) inverting reference clock input (differential) ground; note 1 reference frequency select input 2 (see Table 2) negative supply voltage (−3.3 V); note 3 ground; note 1 STM mode select input 1 (see Table 3) STM mode select input 2 (see Table 3) ground; note 1 STM mode select input 3 (see Table 3) negative supply voltage (−3.3 V); note 3 ground; note 1 data input (differential) inverting data input (differential) ground; note 1 internally connected; note 2 control output for negative power supply ground; note 1 loss of signal detection output internally connected; note 2 4 DESCRIPTION
OQ2541HP; OQ2541U
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE
SYMBOL GND DOUT DOUTQ GND COUT COUTQ GND AREF Notes PIN 41 42 43 44 45 46 47 48 ground; note 1 data output in normal mode (differential) inverted data output in normal mode (differential) ground; note 1 clock output in normal mode (differential) inverted clock output in normal mode (differential) ground; note 1 DESCRIPTION
OQ2541HP; OQ2541U
reference voltage input for controlling voltage swing on data and clock outputs
1. ALL GND pins or pads must be bonded; do not leave one single GND pin or pad unconnected. 2. ALL pins or pads denoted ‘i.c.’ should not be connected. Connections to these pins or pads degrade device performance. 3. ALL VEE pins or pads must be bonded; do not leave one single VEE pin or pad unconnected.
46 COUTQ
45 COUT
42 DOUT
48 AREF
handbook, full pagewidth
43 DOUTQ
38 G.