OR4E4

Preliminary Data Sheet December 2000 ORCA® Series 4 Field-Programmable Gate Arrays Programmable Features s High-performance platform design. — 0.13 µm seven-level metal technology. — Internal performance of >250 MHz (four logic levels). — I/O performance of >416 MHz for all user I/Os. — Over 1.5 million usable system gates. — Meets multiple I/O interface standards. — 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. — Embedded block RAM (EBR) for onboard storage and buffer needs. — Built-in system components including an internal system bus, eight PLLs, and microprocessor interface. Traditional I/O selections. — LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability. 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. — Two slew rates supported (fast and slew-limited). — Fast-capture input latch and input flip-flop (FF)/ latch for reduced input setup time and zero hold time. — Fast open-drain drive capability. — Capability to register 3-state enable signal. — Off-chip clock drive capability. — Two-input function generator in output path. s New programmable high-speed I/O. — Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), zero-bus turn-around (ZBT*), and double data rate (DDR). — Double-ended: LDVS, bused-LVDS, LVPECL. — Customer defined: Ability to substitute arbitrary st...