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PSMN004-25B Dataheets PDF



Part Number PSMN004-25B
Manufacturers Philips
Logo Philips
Description N-channel logic level TrenchMOS transistor
Datasheet PSMN004-25B DatasheetPSMN004-25B Datasheet (PDF)

Philips Semiconductors Product specification N-channel logic level TrenchMOS™ transistor PSMN004-25B, PSMN004-25P FEATURES • ’Trench’ technology • Very low on-state resistance • Fast switching • Low thermal resistance g SYMBOL d QUICK REFERENCE DATA VDSS = 25 V ID = 75 A RDS(ON) ≤ 4.3 mΩ (VGS = 10 V) RDS(ON) ≤ 5 mΩ (VGS = 5 V) s GENERAL DESCRIPTION SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage .

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Philips Semiconductors Product specification N-channel logic level TrenchMOS™ transistor PSMN004-25B, PSMN004-25P FEATURES • ’Trench’ technology • Very low on-state resistance • Fast switching • Low thermal resistance g SYMBOL d QUICK REFERENCE DATA VDSS = 25 V ID = 75 A RDS(ON) ≤ 4.3 mΩ (VGS = 10 V) RDS(ON) ≤ 5 mΩ (VGS = 5 V) s GENERAL DESCRIPTION SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:• d.c. to d.c. converters • switched mode power supplies The PSMN004-25P is supplied in the SOT78 (TO220AB) conventional leaded package. The PSMN004-25B is supplied in the SOT404 surface mounting package. PINNING PIN 1 2 3 tab gate drain1 source drain DESCRIPTION SOT78 (TO220AB) tab SOT404 (D2PAK) tab 2 1 23 1 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Continuous gate-source voltage Peak pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tj ≤ 150 ˚C Tmb = 25 ˚C; VGS = 5 V Tmb = 100 ˚C; VGS = 5 V Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 25 25 ± 15 ± 20 752 752 240 230 175 UNIT V V V V A A A W ˚C 1 It is not possible to make connection to pin:2 of the SOT404 package 2 maximum continuous current limited by package October 1999 1 Rev 1.100 Philips Semiconductors Product specification N-channel logic level TrenchMOS™ transistor THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS PSMN004-25B, PSMN004-25P MIN. - TYP. MAX. UNIT 60 50 0.65 K/W K/W K/W SOT78 package, vertical in still air SOT404 package, pcb mounted, minimum footprint - AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS IAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 75 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 15 V; RGS = 50 Ω; VGS = 5 V MIN. MAX. 120 75 UNIT mJ A ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 4.5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C Gate-source leakage current VGS = ± 10 V; VDS = 0 V; Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 175˚C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal dra.


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