SAA2502

INTEGRATED CIRCUITS DATA SHEET SAA2502 ISO/MPEG Audio Source Decoder Preliminary specification Supersedes data of 1997 Apr 18 File under Integrated Circuits, IC01 1997 Nov 17 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Basic functionality Clock generator module External sample clock Free running internal sample clock Locked internal sample clock Limited sampling frequency support for internal sampling clocks Input interface module Master input mode Slave input mode Buffer controlled input mode Decoder core Frame synchronization to input data streams Master input mode bit rate generation Sample clock generation Decoder precision Scale factor CRC protection Handling of errors in the coded input data Dynamic range compression Baseband audio processing Decoder latency time Output interface module I2S output SPIDF output Bit serial analog output Control interface module Resetting Interrupts Microcontroller interface Initialization Transfer protocols Local registers APPENDIX L3 interface specification Introduction Example of a data transfer Timing requirements Timing 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 L...