SAA4700

INTEGRATED CIRCUITS DATA SHEET SAA4700 VPS dataline processor Preliminary specification File under Integrated Circuits, IC02 March 1991 Philips Semiconductors Preliminary specification VPS dataline processor FEATURES Adaptive sync slicer with buffered composite sync output VCS Adaptive data slicer Data rate clock regenerator Field selection and line 16 decoding Startcode and biphase check Data valid output Storage of data line information in a 40 bit register bank I2C-bus transmission GENERAL DESCRIPTION The SAA4700 is a bipolar integrated circuit designed for use in dataline receivers and incorporates a dataline slicer and decoder. The slicer extracts the dataline signal from the video signal and regenerates the data clock. It also provides signals for the decoder in order to decode the binary data that is transmitted in line 16 of every first field of the composite video signal (video programming signal and video recording programming by Teletext, VPS and VPT systems). The decoded information out of words 5 and 11 to 14 is accessed via the built-in I2C-bus interface. This information then can be used for programming a video cassette recorder in order to start and stop a recording of a television program at the correct aligned time, regardless of a delay or extension in the transmission time of the required program. Tamb QUICK REFERENCE DATA SYMBOL VP IP Vi CVBS PARAMETER supply voltage (pins 15 and 16) total supply current CVBS input signal sync-to-white ...