Document
INTEGRATED CIRCUITS
DATA SHEET
SAA5191 Teletext video processor
Preliminary specification File under Integrated Circuits, IC02 March 1991
Philips Semiconductors
Preliminary specification
Teletext video processor
SAA5191
FEATURES • Adaptive data slicer • Crystal-controlled data clock regeneration with a bit rate of 6.9375 MHz • Adaptive sync separator, horizontal phase detector and 13.5 MHz VCO to provide display phase locked loop (PLL) • TV synchronization at teletext mode
GENERAL DESCRIPTION The SAA5191 is a bipolar integrated circuit that extracts teletext data from the video signal (CVBS), regenerates the teletext clock (TTC) and synchronizes the text display to the television signals (VCS). This device operates in conjunction with the Digital Video Teletext (back-end) Decoder (DVTB - SAA9042A) or any other compatible device.
QUICK REFERENCE DATA SYMBOL VP IP Vi CVBS supply current CVBS input signal on pin 27 (peak-to-peak value) at pin 2 LOW at pin 2 open-circuit Vo VF13 VSYNC VCS outputs signals TTC and TTD (peak-to-peak value, pins 14, 15) 13.5 MHz clock output signal (peak-to-peak value pin 17) SYNC output signal TCS video composite sync level on output pin 25 LOW HIGH Tamb operating ambient temperature − 2.4 0 − − − 0.4 5.5 +70 V V °C − − 2.5 1 1 2.5 3.5 2 − 450 − − 4.5 3 1 650 V V V V V mV PARAMETER supply voltage (pin 16) − − MIN. TYP. 12 70 − − MAX. V mA UNIT
video sync output signal (peak-to-peak value, pin 1) − 200
ORDERING AND PACKAGE INFORMATION EXTENDED TYPE NUMBER SAA5191 Note 1. SOT117-1;1996 November 14 28 PACKAGE PINS DIL PIN POSITION MATERIAL plastic CODE SOT117(1)
March 1991
2
March 1991
handbook, full pagewidth
VP PL CBB VP +12 V 21 19 17 F13 (13.5 MHz clock) 20 18 16
Philips Semiconductors
VCS
25
24
23
22
10
TCS PULSE GENERATOR VCO
Teletext video processor
28 HORIZONTAL PHASE DETECTOR
SENSE "NO INPUT"
SAA5191
LATCHES ADAPTIVE DATA SLICER
15
TTD (data)
composite video input DUAL POLARITY BUFFER CLOCK PHASE DETECTOR
27
ADAPTIVE SYNC SEPARATOR
26 SENSE "NO LOAD" SENSE EXTERNAL DATA
14
TTC (clock)
3
HF LOSS COMPENSATOR 3 4 1 5 6 8 7 9 VP set sync polarity data input
PHASE SHIFTER
12
GAIN SWITCH
OSCILLATOR DIVIDER BY 2 11 XTAL 13.875 MHz 13 GND
VP
2
set video input level
MEH149
sync output
Preliminary specification
SAA5191
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Teletext video processor
PINNING SYMBOL STTV VILS Cfilt Cstore Campl Czero EXD Ctime CCLK CBB XTAL CLF GND TTC TTD VP F13 OSCO CVCR OSCI Chor PL RT CT VCS CBL CVBS TCS Notes 1. Sliced teletext data from external: active HIGH level (current), low impedance input. 2. While the loop is locking up. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DESCRIPTION sync output signal to TV (positive or negative going) level select input of video input (LOW equals 1 V) video filtering capacitor of HF loss compensation HF storage capacitor amplitude capacitor zero level capacitor external data current input (note 1) data timing capacitor for the adaptive data slicer clock phase detector capacitor blanking insertion input 13.875 MHz crystal (double of data rate) 6.9375 MHz clock frequency filter ground (0 V) teletext clock output (for computer controlled teletext) teletext data output (for computer controlled teletext) +12 V supply voltage 13.5 MHz VCO output (for sandcastle generation) oscillator output to series LC-circuit or crystal short time constant capacitor at video recorder mode (note 2) oscillator input from series LC-circuit or crystal horizontal phase capacitor / VCR mode sandcastle input (generated in CCT) timing resistor for pulse generator timing capacitor for pulse generator video composite sync output to CCT black level capacitor composite video input signal from TV text-composite/scan-composite sync input (TSC/SCS)
fpage
SAA5191
PIN CONFIGURATION
STTV 1 VILS 2 Cfilt 3 Cstore 4 Campl 5 Czero 6 EXD 7
28 TCS 27 CVBS 26 CBL 25 VCS 24 CT 23 RT 22 PL
SAA5191
Ctime 8 CCLK 9 CCB 10 XTAL 11 CLF 12 GND 13 TTC 14
MEH150
21 Chor 20 OSCI 19 CVCR 18 OSCO 17 F13 16 VP 15 TTD
Fig.2 Pin configuration.
March 1991
4
Philips Semiconductors
Preliminary specification
Teletext video processor
LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL VP V5 Tstg Tamb voltage on pin 5 storage temperature range operating ambient temperature range PARAMETER supply voltage (pin 16) 0 0 −20 0 MIN.
SAA5191
MAX. 13.2 5.5 125 +70 V V
UNIT
°C °C
CHARACTERISTICS VP = 12 V; Tamb = 25 °C and measurements taken in Fig.3, unless otherwise specified. SYMBOL VP IP Vi CVBS PARAMETER supply voltage range (pin 16) supply current ZS ≤ 250 Ω V2 = LOW V2 = HIGH sync amplitude (peak-to-peak value) data slicing level V2 I2 input voltage LOW (pin 2) input voltage HIGH input current LOW input current HIGH Teletext data output (TTD) V22 phase lock pulse (PL) input voltage (peak-to-peak value, pin 22) data output signal on pin 15 (peak-to-p.