Document
INTEGRATED CIRCUITS
DATA SHEET
SAA4981 Monolithic integrated 16 : 9 compressor
Preliminary specification Supersedes data of May 1994 File under Integrated Circuits, IC02 1995 Oct 05
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
FEATURES • Fixed horizontal compression by a factor of video standards • 5 MHz bandwidth • Bypass function • Inputs for luminance and chrominance of side panels • Standard video inputs and outputs (Y, (B−Y) and (R−Y)) • Horizontal and vertical sync signals are not processed • Pre filters and post filters on chip. GENERAL DESCRIPTION The integrated 16 : 9 compressor is an IC which compresses the active part of a video line by a factor of 4⁄3 from, for example, 52 µs to 39 µs. This is necessary to display 4:3 video software on a 16 : 9 tube in the correct proportion. The capacitively coupled video inputs are Y, (B−Y) and (R−Y).
4⁄ 3
SAA4981
for most
• Three fixed screen positions (left, centre and right)
The synchronisation input HREF is a line frequency reference signal. The bandwidth of the IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y, (B−Y) and (R−Y) and provides the following two possibilities: 1. Bypass function (the input signal is not compressed) 2. Compressed video by a factor of 4⁄3 with three different fixed screen positions (left, centre and right). The luminance and chrominance of the side panels are determined by the external signals YSIDE, BYSIDE and RYSIDE. The horizontal compression is a time discrete and amplitude continuous signal processing. This provides pre and post filters which are realized on-chip. The internal clock generation is achieved with a 54 MHz horizontal PLL which is synchronized to the positive edge of the HREF signal. The function of the IC is controlled by the three control signals CTRL1, CTRL2 and CTRL3.
QUICK REFERENCE DATA Voltages for video signals are peak-to-peak values for 75% colour bars. All voltages are referenced to VEEA = VEED = 0 V. SYMBOL VCCA VCCD ViY(p-p) ViU(p-p) ViV(p-p) ViHREF VoY(p-p) VoU(p-p) VoV(p-p) PARAMETER analog supply voltage digital supply voltage Y input voltage (peak-to-peak value) (B−Y) input voltage (peak-to-peak value) (R−Y) input voltage (peak-to-peak value) input HREF top pulse YOUT output voltage (peak-to-peak value) (B−Y)OUT output voltage (peak-to-peak value) (R−Y)OUT output voltage (peak-to-peak value) MIN. 4.75 4.75 − − − 3.0 − − − TYP. 5.0 5.0 0.32 1.33 1.05 − 0.32 1.33 1.05 MAX. 5.5 5.5 0.45 1.9 1.5 6.5 0.5 2.1 1.7 V V V V V V V V V UNIT
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA4981 SAA4981T DIP24 SO24 DESCRIPTION plastic dual in-line package; 24 leads (600 mil) plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT101-1 SOT137-1
1995 Oct 05
2
CTRL1
CTRL3
handbook, full pagewidth
1995 Oct 05
23 YIN CLAMP 5 MHz LOW-PASS FILTER 22 (B-Y)IN CLAMP 5 MHz LOW-PASS FILTER
BLOCK DIAGRAM
Philips Semiconductors
Monolithic integrated 16 : 9 compressor
VCCA
VEEA
VCCD
VEED
SUB
20
19
8
7
4
SC LINE MEMORY
SC LINE MEMORY
MUX SC LINE MEMORIES
6.7 MHz LOW-PASS FILTER
MUX Y
18
YOUT
SAA4981
C1 C2 C3
SC LINE MEMORY
SC LINE MEMORY
MUX SC LINE MEMORIES
6.7 MHz LOW-PASS FILTER
MUX BY
17
(B-Y)OUT
C1
C2
C3
3
21 (R-Y)IN CLAMP 5 MHz LOW-PASS FILTER HREF 6 HORIZONTAL SEPARATION C1 CONTROLLER 54 MHz PLL C2 C3 12 TEST 9 10 CTRL2 11
SC LINE MEMORY
SC LINE MEMORY
MUX SC LINE MEMORIES
6.7 MHz LOW-PASS FILTER MUX RY
16
(R-Y)OUT
3
C1
C2
C3
3 CLAMP REFERENCE
1
2
3
24
5
15
14
13
MHA277
Preliminary specification
BYSIDE RYSIDE YSIDE CLMY CLMBY CLMRY CLAOUT BGREF
SAA4981
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
PINNING SYMBOL CLMY CLMBY CLMRY SUB CLAOUT HREF VEED VCCD CTRL1 CTRL2 CTRL3 TEST RYSIDE BYSIDE YSIDE (R−Y)OUT (B−Y)OUT YOUT VEEA VCCA (R−Y)IN (B−Y)IN YIN BGREF PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION decoupling capacitor for Y reference voltage decoupling capacitor for BY reference voltage decoupling capacitor for RY reference voltage substrate connection (see Fig.5) internal clamping reference voltage output horizontal reference input ground for digital section positive digital supply voltage control input 1 control input 2 control input 3 test mode activation side panel input for RY side panel input for BY side panel input for Y output signal for (R−Y) output signal for (B−Y) output signal for Y ground for analog section positive analog supply voltage input signal for (R−Y) input signal for (B−Y) input signal for Y decoupling capacitor for internal reference voltage Fig.2 Pin configuration.
handbook, halfpage CLMY
SAA4981
1 2 3 4 5 6
24 BGREF 23 YIN 22 (B-Y)IN 21 (R-Y)IN 20 VCCA
CLMBY CLMRY SUB CLAOUT HREF VEED VCCD CTRL1
SAA4981
7 8 9
19 VEEA 18 YOUT 17 (B−Y)OUT 16 (R−Y.