Document
BSI
FEATURES
Very Low Power/Voltage CMOS SRAM 512K X 16 bit (Single CE Pin)
DESCRIPTION
BS616LV8010
• Vcc operation voltage : 2.7~3.6V • Very low power consumption : Vcc = 3.0V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade: 25mA (@70ns) operating current 1.5uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV8010 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits and operates from a range of 2.7V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1.5uA at 3V/25oC and maximum access time of 55ns at 3V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE) ,active LOW output enable(OE) and three-state output drivers. The BS616LV8010 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8010 is available in 48B BGA and 44L TSOP2 packages.
PRODUCT FAMILY
PRODUCT FAMILY BS616LV8010EC BS616LV8010FC BS616LV8010EI BS616LV8010FI OPERATING TEMPERATURE +0 C to +70 C -40 O C to +85O C
O O
Vcc RANGE 2.7V ~ 3.6V 2.7V ~ 3.6V
SPEED ( ns )
55ns : 3.0~3.6V 70ns : 2.7~3.6V
( I CCSB1, Max )
POWER DISSIPATION STANDBY Operating
( ICC , Max )
PKG TYPE TSOP2-44 BGA-48-0912 TSOP2-44 BGA-48-0912
Vcc=3V
Vcc=3V
55ns
Vcc=3V
70ns
55 / 70 55 / 70
5uA 10uA
30mA 31mA
24mA 25mA
PIN CONFIGURATIONS
A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8 A8 A9 A10 A11 A12 A13
BLOCK DIAGRAM
A4 A3 A2 A1 A0 A17 A16 A15 A14 A13 A12 Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 x 4096
BS616LV8010EC BS616LV8010EI
4096 D0 16 Data Input Buffer 16 Column I/O
1
2
OE UB D10 D11 D12 D13 NC . A8
3
A0 A3 A5 A17 VSS A 14 A12 A9
4
A1 A4 A6 A7 A16 A 15 A 13 A 10
5
A2 CE D1 D3 D4 D5 WE A 11
6
NC D0 D2 V CC V SS D6 D7 NC
A B C D E F G H
LB D8 D9 V SS V CC D14 D15 A 18
. . . .
D15
. . . .
Write Driver
Sense Amp 256 Column Decoder
16
Data Output
16
Buffer
CE WE OE UB LB Vcc Vss Control
16 Address Input Buffer
A11 A10 A9 A8 A7 A6 A5 A18
48-Ball CSP top View
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8010
1
Revision 1.1 Jan. 2004
BSI
PIN DESCRIPTIONS
BS616LV8010
Function
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM. CE is act.