Limiting Amp. ADN2819 Datasheet

ADN2819 Amp. Datasheet pdf. Equivalent

Part ADN2819
Description Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
Feature Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2819 FEATURES Meets.
Manufacture Analog Devices
Datasheet
Download ADN2819 Datasheet



ADN2819
Multirate to 2.7 Gb/s Clock and Data
Recovery IC with Integrated Limiting Amp
ADN2819
FEATURES
PRODUCT DESCRIPTION
Meets SONET requirements for jitter
transfer/generation/tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
1.9 GHz minimum bandwidth
Patented clock recovery architecture
Loss of signal detect range: 3 mV to 15 mV
Single reference clock frequency for all rates, including
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK
LVPECL/LVDS/LVCMOS/LVTTL compatible inputs
(LVPECL/LVDS only at 155.52 MHz)
19.44 MHz oscillator on-chip to be used with external crystal
The ADN2819 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at rates of OC-3,
OC-12, OC-48, Gigabit Ethernet, and 15/14 FEC rates. All
SONET jitter requirements are met, including jitter transfer,
jitter generation, and jitter tolerance. All specifications are
quoted for –40°C to +85°C ambient temperature, unless
otherwise noted.
The device is intended for WDM system applications, and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both native rates and 15/14 rate
digital wrappers are supported by the ADN2819, without any
change of reference clock.
Loss of lock indicator
This device, together with a PIN diode and a TIA preamplifier,
Loopback mode for high speed test data
can implement a highly integrated, low cost, low power, fiber
Output squelch and bypass features
optic receiver.
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm 48-lead LFCSP
APPLICATIONS
SONET OC-3/-12/-48, SDH STM-1/-4/-16, GbE and 15/14
FEC rates
WDM transponders
Regenerators/repeaters
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
The ADN2819 is available in a compact 7 mm × 7 mm, 48-lead
chip scale package.
Test equipment
Backplane applications
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N
VCC VEE
CF1 CF2
LOL
2 ADN2819
PIN
QUANTIZER
NIN
PHASE
SHIFTER
PHASE
DET.
LOOP
FILTER
LOOP
FILTER
VCO
FREQUENCY
LOCK
DETECTOR
VREF
LEVEL
DETECT
THRADJ SDOUT
DATA
RETIMING
2
DATAOUTP/N
DIVIDER
1/2/4/16
2
CLKOUTP/N
FRACTIONAL
DIVIDER
3
SEL[0..2]
2
2
/n
XTAL
OSC
REFSEL[0..1]
REFCLKP/N
XO1
XO2
REFSEL
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.



ADN2819
ADN2819
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Definition of Terms.......................................................................... 9
Maximum, Minimum, and Typical Specifications ................... 9
Input Sensitivity and Input Overdrive....................................... 9
Single-Ended vs. Differential ...................................................... 9
LOS Response Time ................................................................... 10
Jitter Specifications..................................................................... 10
Theory of Operation ...................................................................... 12
Functional Description .................................................................. 14
Multirate Clock and Data Recovery......................................... 14
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format..............................................................Universal
Changes to Specifications ............................................................ 3
Changes to Table 7 and Table 8................................................. 15
Updated Outline Dimensions ................................................... 21
Changes to Ordering Guide ...................................................... 21
1/03—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Table IV ................................................................... 12
Updated OUTLINE DIMENSIONS ........................................ 16
Limiting Amplifier ..................................................................... 14
Slice Adjust .................................................................................. 14
Loss of Signal (LOS) Detector .................................................. 14
Reference Clock.......................................................................... 14
Lock Detector Operation .......................................................... 15
Squelch Mode ............................................................................. 16
Test Modes: Bypass and Loopback........................................... 16
Applications Information .............................................................. 17
PCB Design Guidelines ............................................................. 17
Choosing AC-Coupling Capacitors ......................................... 19
DC-Coupled Application .......................................................... 20
LOL Toggling During Loss of Input Data............................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
Rev. B | Page 2 of 24





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