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28C256 Dataheets PDF



Part Number 28C256
Manufacturers Catalyst
Logo Catalyst
Description 32K-Bit Parallel E2PROM
Datasheet 28C256 Datasheet28C256 Datasheet (PDF)

CAT28C256 32K-Bit Parallel E2PROM FEATURES s Fast Read Access Times: 120/150ns s Low Power CMOS Dissipation: s Hardware and Software Write Protection s Automatic Page Write Operation: –Active: 25 mA Max. –Standby: 150 µA Max. s Simple Write Operation: –1 to 64 Bytes in 5ms –Page Load Timer s End of Write Detection: –On-Chip Address and Data Latches –Self-Timed Write Cycle with Auto-Clear s Fast Write Cycle Time: –Toggle Bit –DATA Polling s 100,000 Program/Erase Cycles s 100 Year Data Retenti.

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CAT28C256 32K-Bit Parallel E2PROM FEATURES s Fast Read Access Times: 120/150ns s Low Power CMOS Dissipation: s Hardware and Software Write Protection s Automatic Page Write Operation: –Active: 25 mA Max. –Standby: 150 µA Max. s Simple Write Operation: –1 to 64 Bytes in 5ms –Page Load Timer s End of Write Detection: –On-Chip Address and Data Latches –Self-Timed Write Cycle with Auto-Clear s Fast Write Cycle Time: –Toggle Bit –DATA Polling s 100,000 Program/Erase Cycles s 100 Year Data Retention s Commerical, Industrial and Automotive –5ms Max s CMOS and TTL Compatible I/O Temperature Ranges DESCRIPTION The CAT28C256 is a fast, low power, 5V-only CMOS parallel E2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with autoclear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the selftimed write cycle. Additionally, the CAT28C256 features hardware and software write protection. The CAT28C256 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC packages. BLOCK DIAGRAM A6–A14 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 32,768 x 8 E2PROM ARRAY 64 BYTE PAGE REGISTER VCC HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER 5096 FHD F02 I/O0–I/O7 A0–A5 ADDR. BUFFER & LATCHES © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25020-0A 2/98 CAT28C256 PIN CONFIGURATION DIP Package (P) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC Package (N) A14 NC VCC WE A13 29 28 27 26 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 A7 A12 4 3 2 1 32 31 30 A8 A9 A11 NC OE A10 CE I/O7 I/O6 9 25 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 VSS NC I/O3 I/O4 I/O5 I/O1 I/O2 5096 FHD F01 TSOP Package (8mm X 13.4mm) (T13) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 28C256 F03 PIN FUNCTIONS Pin Name A0–A14 I/O0–I/O7 CE OE Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Pin Name WE VCC VSS NC Function Write Enable 5V Supply Ground No Connect Doc. No. 25020-0A 2/98 2 CAT28C256 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND(1) TDR(1) VZAP(1) ILTH(1)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 104 or 105 100 2000 100 Max. *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Units Cycles/Byte Years Volts mA Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Limits Symbol ICC ICCC(5) ISB ISBC(6) ILI ILO VIH(6) VIL(5) VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Operating, CMOS) VCC Current (Standby, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage 3.5 –10 –10 2 –0.3 2.4 0.4 Min. Typ. Max. 30 25 1 150 10 10 VCC +0.3 0.8 Units mA mA mA µA µA µA V V V V V IOH = –400µA IOL = 2.1mA Test Conditions CE = OE = VIL, f=8MHz All I/O’s Open CE = OE = VILC, f=8MHz All I/O’s Open CE = VIH, All I/O’s Open CE = VIHC, All I/O’s Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may ove.


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