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28C64 Dataheets PDF



Part Number 28C64
Manufacturers ATMEL
Logo ATMEL
Description 64K 8K x 8 CMOS E2PROM
Datasheet 28C64 Datasheet28C64 Datasheet (PDF)

Features • Fast Read Access Time – 120 ns • Fast Byte Write – 200 µs or 1 ms • Self-timed Byte Write Cycle – Internal Address and Data Latches – Internal Control Timer – Automatic Clear Before Write • Direct Microprocessor Control – READY/BUSY Open Drain Output – DATA Polling • Low Power – 30 mA Active Current – 100 µA CMOS Standby Current • High Reliability – Endurance: 104 or 105 Cycles – Data Retention: 10 Years • 5V ± 10% Supply • CMOS and TTL Compatible Inputs and Outputs • JEDEC Approved B.

  28C64   28C64



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Features • Fast Read Access Time – 120 ns • Fast Byte Write – 200 µs or 1 ms • Self-timed Byte Write Cycle – Internal Address and Data Latches – Internal Control Timer – Automatic Clear Before Write • Direct Microprocessor Control – READY/BUSY Open Drain Output – DATA Polling • Low Power – 30 mA Active Current – 100 µA CMOS Standby Current • High Reliability – Endurance: 104 or 105 Cycles – Data Retention: 10 Years • 5V ± 10% Supply • CMOS and TTL Compatible Inputs and Outputs • JEDEC Approved Byte-wide Pinout • Commercial and Industrial Temperature Ranges Description The AT28C64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile electrically erasable and programmable read only memory with popular, easy-to-use features. The device is manufactured with Atmel’s reliable nonvolatile technology. (continued) Pin Configurations Pin Name A0 - A12 CE OE WE I/O0 - I/O7 RDY/BUSY NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy Output No Connect Don’t Connect TSOP Top View PDIP, SOIC Top View RDY/BUSY (or NC) 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14 28 VCC 27 WE 26 NC 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 LCC, PLCC Top View 64K (8K x 8) Parallel EEPROMs AT28C64 AT28C64X 4 A7 3 A12 2 RDY/BUSY (or NC) 1 DC 32 VCC 31 WE 30 NC OE 1 A11 2 A9 3 A8 4 NC 5 WE 6 VCC 7 RDY/BUSY (or NC) 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14 28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13 29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6 I/O1 14 I/O2 15 VSS 16 DC 17 I/O3 18 I/O4 19 I/O5 20 Note: PLCC package pins 1 and 17 are DON’T CONNECT. Rev. 0001H–12/99 1 The AT28C64 is accessed like a Static RAM for the read or write cycles without the need for external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY (unless pin 1 is N.C.) and DATA Polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. The CMOS technology offers fast access times of 120 ns at low power dissipation. When the chip is deselected the standby current is less than 100 µA. Atmel’s AT28C64 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved data retention characteristics. An extra 32 bytes of EEPROM are available for device identification or tracking. Block Diagram Absolute Maximum Ratings* Temperature under Bias ........................


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