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28F008SA-L Dataheets PDF



Part Number 28F008SA-L
Manufacturers Intel
Logo Intel
Description 8-MBIT (1 MBIT x 8) FLASHFILETM MEMORY
Datasheet 28F008SA-L Datasheet28F008SA-L Datasheet (PDF)

28F008SA-L 8-MBIT (1 MBIT x 8) FLASHFILE TM MEMORY Y High-Density Symmetrically-Blocked Architecture Sixteen 64-Kbyte Blocks Low-Voltage Operation b 3 3V g 0 3V or 5 0V g 10% VCC Extended Cycling Capability 10 000 Block Erase Cycles 160 000 Block Erase Cycles per Chip Automated Byte Write and Block Erase Command User Interface Status Register System Performance Enhancements RY BY Status Output Erase Suspend Capability Y High-Performance Read 200 ns Maximum Access Time Deep Power-Down Mode 0 2.

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28F008SA-L 8-MBIT (1 MBIT x 8) FLASHFILE TM MEMORY Y High-Density Symmetrically-Blocked Architecture Sixteen 64-Kbyte Blocks Low-Voltage Operation b 3 3V g 0 3V or 5 0V g 10% VCC Extended Cycling Capability 10 000 Block Erase Cycles 160 000 Block Erase Cycles per Chip Automated Byte Write and Block Erase Command User Interface Status Register System Performance Enhancements RY BY Status Output Erase Suspend Capability Y High-Performance Read 200 ns Maximum Access Time Deep Power-Down Mode 0 20 mA ICC Typical SRAM-Compatible Write Interface Hardware Data Protection Feature Erase Write Lockout during Power Transitions Industry Standard Packaging 40-Lead TSOP 44-Lead PSOP ETOX TM III Nonvolatile Flash Technology 12V Byte Write Block Erase Y Y Y Y Y Y Y Y Y Intel’s 28F008SA-L 8 Mbit FlashFile TM Memory is the highest density nonvolatile read write solution for solidstate storage The 28F008SA-L’s extended cycling symmetrically-blocked architecture fast access time write automation and very low power consumption provide a more reliable lower power lighter weight and higher performance alternative to traditional rotating disk technology The 28F008SA-L brings new capabilities to portable computing Application and operating system software stored in resident flash memory arrays provide instant-on rapid execute-in-place and protection from obsolescence through in-system software updates Resident software also extends system battery life and increases reliability by reducing disk drive accesses For high-density data acquisition applications the 28F008SA-L offers a more cost-effective and reliable alternative to SRAM and battery Traditional high-density embedded applications such as telecommunications can take advantage of the 28F008SA-L’s nonvolatility blocking and minimal system code requirements for flexible firmware and modular software designs The 28F008SA-L is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write The 28F008SA-L memory map consists of 16 separately erasable 64-Kbyte blocks Intel’s 28F008SA-L employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity Its 200 ns access time provides superior performance when compared with magnetic storage media A deep power-down mode lowers power consumption to 0 66 mW typical thru VCC crucial in portable computing handheld instrumentation and other low-power applications The RP power control input also provides absolute data protection during system power-up down Manufactured on Intel’s 0 8 micron ETOX process the 28F008SA-L provides the highest levels of quality reliability and cost-effectiveness Other brands and names are property of their respective owners Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 December 1995 Order Number 290435-005 28F008SA-L The Status Register indicates the status of the WSM and when the WSM successfully completes the desired byte write or block erase operation The RY BY output gives an additional indicator of WSM activity providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase for example) Status polling using RY BY minimizes both CPU overhead and system power consumption When low RY BY indicates that the WSM is performing a block erase or byte write operation RY BY high indicates that the WSM is ready for new commands block erase is suspended or the device is in deep powerdown mode Maximum access time is 200 ns (tACC) over the commercial temperature range (0 C to a 70 C) and over VCC supply voltage range (3 0V to 3 6V and 4 5V to 5 5V) ICC active current (CMOS Read) is 5 mA typical 12 mA maximum at 5 MHz 3 3V g 0 3V When the CE and RP pins are at VCC the ICC CMOS Standby mode is enabled A Deep Powerdown mode is enabled when the RP pin is at GND minimizing power consumption and providing write protection ICC current in deep powerdown is 0 20 mA typical Reset time of 500 ns is required from RP switching high until outputs are valid to read attempts Equivalently the device has a wake time of 1 ms from RP high until writes to the Command User Interface are recognized by the 28F008SA-L With RP at GND the WSM is reset and the Status Register is cleared PRODUCT OVERVIE.


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