Document
Freescale Semiconductor, Inc.
Chip Errata DSP56301 Digital Signal Processor Mask: 2K30A
General remark: In order to prevent the use of instructions or sequences of instructions that do not operate correctly, we encourage you to use the “lint563” program to identify such cases and use alternative sequences of instructions. This program is available as part of the Motorola DSP Tools CLAS package.
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Silicon Errata Errata Number Errata Description Description (added 8/16/2001): Some K30A devices shipped under an XC part number are subject to a problem if operated in DMA mode 5. The problem occurs if two consecutive host commands are sent to the DSP. The second host command is received, the corresponding answer message is composed, and the DMA channel is set up correctly to transmit the message to the host. However, the message is never sent. The host port status register shows a host transmit data request (bit HTRQ in HSTR is set.) DTDn is never set, indicating there has been no terminated transfer. Sequences of: 1. data, 2. host command to terminate the transfer, and 3. acknowledgement from the host work properly and can be repeated as often as needed. If a second host command is sent to the DSP, without first sending data, the DMA channel locks up. This problem has proven to be low level to date, occurring at a rate of about 350 ppm. The product’s performance regarding this issue does not drift over time; that is, it is not a reliability risk. The problem can also be manifested in other modes when more than one DMA channel is operating, with two or more channels moving data while one is servicing the PCI FIFO. In this case, the channel servicing the PCI FIFO stalls and the PCI bus enters an endless state of retries. Applies to Mask 2K30A
ES133
Motorola Semiconductor Products Sector 301CE2K30A_0_8 6501 William Cannon Drive West, Austin, 78735-8598 For More Texas Information On This Product, Go to: www.freescale.com
ng 12/19/02 pg. 1 1996-2002 Motorola
Freescale Semiconductor, Inc.
Chip Errata DSP56301 Digital Signal Processor Mask:2K30A
Documentation Errata Errata Number Document Update Description (revised 11/9/98): XY memory data move does not work properly if the X-memory move destination is internal I/O and the Y-memory move source is a register used as destination in the previous adjacent move from non Y-memory OR the Y-memory move destination is a register used as source in the next adjacent move to non Y-memory. Here are examples of the two cases (where x:(r1) is a peripheral): Example 1: ED1
move #$12,y0 move x0,x:(r7) y0,y:(r3) (while x:(r7) is a peripheral).
Applies to Mask 2K30A
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Example 2:
mac move x1,y0,a x1,x:(r1)+ y0,y1 y:(r6)+,y0
This is not a bug, but a documentation update. Any of the following alternatives can be used: a. Separate these two consecutive moves by any other instruction. b. Split XY Data Move to two moves. Description (added 10/09/1997): ED2 BL pin timings T198 and T199 in the Data Sheet are changed, improving the arbitration latency: T198 is 5 ns (max), T199 is 0 ns (min). This is not a bug, but a documentation update. Description (added 10/09/1997): ED3 A one-word conditional branch instruction at LA-1 is not allowed. This is not a bug, but a documentation update. 2K30A 2K30A
DSP56301 Errata 1996-2002, Motorola
301CE2K30A_0_8 For More Information On This Product, Go to: www.freescale.com
ng 12/19/02 pg. 2
Freescale Semiconductor, Inc.
Chip Errata DSP56301 Digital Signal Processor Mask:2K30A
Errata Number
Document Update Description (added 10/09/1997): The following instructions should not start at address LA:
Applies to Mask 2K30A
ED4
MOVE to/from Program space {MOVEM, MOVEP (only the P space options)} This is not a bug but a documentation update (Appendix B, DSP56300 Family Manual). Description (added 4/13/98):
Freescale Semiconductor, Inc...
2K30A
ED6
When the HIRQ pin is used in pulse mode (HIRH=0 in DCTR), the LT[7:0] value (in CLAT) should not be zero. This is not a bug but a documentation update. Description (added 1/27/98): When activity passes from one DMA channel to another and the DMA interface accesses external memory (which requires one or more wait states), the DACT and DCH status bits in the DMA Status Register (DSTR) may indicate improper activity status for DMA Channel 0 (DACT = 1 and DCH[2:0] = 000). Workaround: None. Pertains to: DSP56300 Family Manual, Sections 8.1.6.3 and 8.1.6.4 Description (added 10/09/1997): The timing for HSAK is no longer qualified by the data strobe. The new timing numbers are: 2K30A 2K30A
ED7
ED8
a. T318—HSAK assertion from HA0–HA10 and HAEN valid is 30.0 ns maximum. b. T319—HSAK assertion hold from HA0-HA10 and NAEN not valid is 2.0 ns minimum. This is not a bug, but a documentation update of a specification change.
DSP56301 Errata 1996-2002, Motorola
301CE2K30A_0_8 For More Information On This Product, Go to: www.freescale.com
ng 12/1.