Document
54F 74F182 Carry Lookahead Generator
December 1994
54F 74F182 Carry Lookahead Generator
General Description
The ’F182 is a high-speed carry lookahead generator It is generally used with the ’F181 or ’F381 4-bit arithmetic logic units to provide high-speed lookahead over word lengths of more than four bits
Features
Y Y
Y
Provides lookahead carries across a group of four ALUs Multi-level lookahead high-speed arithmetic operation over long word lengths Guaranteed 4000V minimum ESD protection
Commercial 74F182PC
Military
Package Number N16E
Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
54F182DM (Note 2) 74F182SJ (Note 1) 54F182FM (Note 2) 54F182LM (Note 2)
J16A M16D W16A E20A
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC
TL F 9492 – 1 TL F 9492 – 2 TL F 9492–6
TL F 9492–3
TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9492 RRD-B30M105 Printed in U S A
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 20 1 0 14 0 1 0 16 0 10 80 10 80 10 60 10 40 50 33 3 50 33 3 50 33 3 Input IIH IIL Output IOH IOL 20 mA b1 2 mA 20 mA b8 4 mA 20 mA b9 6 mA 20 mA b4 8 mA 20 mA b4 8 mA 20 mA b3 6 mA 20 mA b2 4 mA b 1 mA 20 mA b 1 mA 20 mA b 1 mA 20 mA
Cn G0 G2 G1 G3 P0 P1 P2 P3 Cn a xbCn a z G P
Carry Input Carry Generate Inputs (Active LOW) Carry Generate Input (Active LOW) Carry Generate Input (Active LOW) Carry Propagate Inputs (Active LOW) Carry Propagate Input (Active LOW) Carry Propagate Input (Active LOW) Carry Outputs Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW)
Functional Description
The ’F182 carry lookahead generator accepts up to four pairs of Active LOW Carry Propagate (P0 – P3) and Carry Generate (G0 – G3) signals and an Active HIGH Carry input (Cn) and provides anticipated Active HIGH carries (Cn a x Cn a y Cn a z) across four groups of binary adders The ’F182 also has Active LOW Carry Propagate (P) and Carry Generate (G) outputs which may be used for further levels of lookahead The logic equations provided at the outputs are Cn a x e G0 a P0Cn Cn a y Cn a z G P
e G1 a P1G0 a P1P0Cn e G2 a P2G1 a P2P1G0 a P2P1P0Cn e G3 a P3G2 a P3P2G1 a P3P2P1G0 e P2P2P1P0
Also the ’F182 can be used with binary ALUs in an active LOW or active HIGH input operand mode The connections (Figure 1) to and from the ALU to the carry lookahead generator are identical in both cases Carries are rippled between lookahead blocks The critical speed path follows the circled numbers There are several possible arrangements for the carry interconnects but all achieve about the same speed A 28-bit ALU is formed by dropping the last ’F181 or ’F381
TL F 9492 – 5
FIGURE 1 32-Bit ALU with Rippled Carry between 16-Bit Lookahead ALUs
ALUs may be either ’F181 or ’F381
2
Truth Table
Inputs Cn X L X H X X L X X H X X X L X X X H G0 H H L X X H H X L X X X H H X X L X X X X H X X X L H X X X L P0 H X X L X H X X X L X X H X X X X L H H H L X X X H H H X L X X X X H H X X L X H X X X L L X H X X X X L L X X H X X X X L X H X X L H H H H L X X X X H H H X L X X H X X X X L L L X H X X X X L L X X H X L H H H H L X X X H X X X X L L L X X X H L G1 P1 G2 P2 G3 P3 Cn a x L L H H L L L H H H L L L L H H H H H H H H L L L L H H H H L Outputs Cn a y Cn a z G P
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial
Logic Diagram
TL F 9492 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
3
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin
b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150
Recommended Operating Conditions
Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial
b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V
C C C C
b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 E.