74F193

74F193 Up/Down Binary Counter with Separate Up/Down Clocks April 1988 Revised July 1999 74F193 Up/Down Binary Counter with Separate Up/Down Clocks General Description The 74F193 is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Ordering Code: Order Number 74F193SC 74F193SJ 74F193PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009497 www.fairchildsemi.com 74F193 Unit Loading/Fan Out U.L. Pin Names CPU CPD MR PL P0–P3 Q0–Q3 TCD TCU Description HIGH/LOW Count Up Clock Input (Active Rising Edge) Count Down Clock In...