74F219A

INTEGRATED CIRCUITS 74F219A 64-bit TTL bipolar RAM, non-inverting (3-State) Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Philips Semiconductors Product specification 64-bit TTL bipolar RAM, non-inverting (3-State) 74F219A FEATURES High speed performance Replaces 74F219 Address access time: 8ns max vs 28ns for 74F219 Power dissipation: 4.3mW/bit typ Schottky clamp TTL One chip enable Non–Inverting outputs (for inverting outputs see 74F189A) 3–state outputs 74F219A in 150 mil wide SO is preferred options for new designs C3F219A in 300 mil wide SOL replaces 74F219 in existing designs APPLICATIONS Scratch pad memory Buffer memory Push down stacks Control store PIN CONFIGURATION A0 1 CE 2 WE 3 D0 4 Q0 5 D1 6 16 VCC 15 A1 14 A2 13 A3 12 D3 11 Q3 10 D2 9 Q2 DESCRIPTION The 74F219A is a high speed, 64–bit RAM organized as a 16–word by 4–bit array. Address inputs are buffered to minimize loading and are fully decoded on chip. The outputs are in high impedance state whenever the chip enable (CE) is high. The outputs are active only in the READ mode (WE = high) and the output data is the complement of the stored data. Q1 7 GND 8 SF00307 TYPE 74F219A TYPICAL ACCESS TIME 5.0ns TYPICAL SUPPLY CURRENT(TOTAL) 55mA ORDERING INFORMATION ORDER CODE DESCRIPTION 16-pin plastic Dual In-line Package 16-pin plastic Small Outline (150mil) 16-pin plastic Small Outline Large (300mil) COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C t...