Octal Transparent Latch
54F 74F373 Octal Transparent Latch with TRI-STATE Outputs
May 1995
54F 74F373 Octal Transparent Latch with TRI-STATE O...
Description
54F 74F373 Octal Transparent Latch with TRI-STATE Outputs
May 1995
54F 74F373 Octal Transparent Latch with TRI-STATE Outputs
General Description
The ’F373 consists of eight latches with TRI-STATE outputs for bus organized system applications The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH When LE is LOW the data that meets the setup times is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state
Features
Y Y Y
Eight latches in a single package TRI-STATE outputs for bus interfacing Guaranteed 4000V minimum ESD protection
Commercial 74F373PC
Military
Package Number N20A
Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Molded Shrink Small Outline EIAJ Type II 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
54F373DM (QB) 74F373SC (Note 1) 74F373SJ (Note 1) 74F373MSA (Note 1) 54F373FM (QB) 54F373LM (QB)
J20A M20B M20D MSA20 W20A E20A
Note 1 Devices also available in 13 reel Use suffix e SCX SJX and MSAX
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment for DIP SOIC SSOP and Flatpak Pin Assignment for LCC
TL F 9523 – 3 TL F 9523–4 TL F 9523 – 2
TL F 9523–1
TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9523 RRD-B30M75 Printed in U S...
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