74F378

INTEGRATED CIRCUITS 74F378 Hex D flip-flop with enable Product specification IC15 Data Handbook 1989 Oct 05 Philips Semiconductors Philips Semiconductors Product specification Hex D flip-flop with enable 74F378 FEATURES 6-bit high-speed parallel register Positive edge-triggered D-type inputs Fully buffered common Clock and Enable inputs Input clamp diodes limit high speed termination effects Fully TTL and CMOS compatible DESCRIPTION The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transformed to the corresponding flop-flop’s Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation. TYPE 74F378 TYPICAL fmax 100MHz TYPICAL SUPPLY CURRENT (TOTAL) 35mA ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F378N N74F378D PKG DWG # 16–pin plastic DIP 16–pin plastic SO SOT38-4 SOT109-1 PIN CONFIGURATION E 1 Q0 2 D0 3 D1 4 Q1 5 D2 6 Q2 7 GND 8 16 V CC 15 Q5 14 D5 13 D4 12 Q4 11 D3 10 Q3 9 CP SF00927 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS D0 – D5 CP E Data inputs Clock pulse input (active rising edge) Enable input (active low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/3...