74F378

74F378 Parallel D-Type Register with Enable April 1988 Revised August 1999 74F378 Parallel D-Type Register with Enable General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features s 6-bit high-speed parallel register s Positive edge-triggered D-type inputs s Fully buffered common clock and enable inputs s Input clamp diodes limit high-speed termination effects s Full TTL and CMOS compatible Ordering Code: Order Number 74F378SC 74F378SJ 74F378PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009526 www.fairchildsemi.com 74F378 Unit Loading/Fan Out U.L. Pin Names E D0–D5 CP Q0–Q5 Description HIGH/LOW Enable Input (Active LOW) Data Inputs Clock Pulse Input (Active Rising Edge) Outputs 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Functional Description The 74F378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q inputs. The Clock (CP) and Enable (E) ...