74F379A

INTEGRATED CIRCUITS 74F379A Quad register Product specification IC15 Data Handbook 1996 Mar 12 Philips Semiconductors Philips Semiconductors Product specification Quad register 74F379A FEATURES Edge–triggered D–type inputs Buffered positive edge–triggered clock Buffered common enable input True and complementary outputs Offers light loading PNP inputs (IIL = –20µA) TYPE 74F379A TYPICAL fmax 200MHz DESCRIPTION The 74F379A is a 4–bit register with buffered common enable (E). This device is similar to the 74F175A but features the common enable rather than common master reset. TYPICAL SUPPLY CURRENT (TOTAL) 29mA ORDERING INFORMATION ORDER CODE DESCRIPTION 16–pin plastic DIP 16–pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F379AN N74F379AD PKG, DWG. # SOT38–4 SOT109–1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE TYPE PINS D0 – D3 74F379A CP E Q0 – Q3 Data inputs Clock pulse input (active rising edge) Enable input (active low) True outputs DESCRIPTION 74F (U.L.) HIGH/ LOW 1.0/0.033 1.0/0.033 1.0/0.033 50/33 50/33 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 1.0mA/20mA 15mA/20mA Q0 – Q3 Complementary outputs Note to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION E Q0 Q0 D0 D1 Q1 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q3 Q3 D3 D2 Q2 Q2 CP LOGIC SYMBOL 4 5 12 13 D0 D1 D2 D3 9 1 CP E Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 3 VCC = ...