74F385

Philips Semiconductors Product specification Quad serial adder/subtractor 74F385 FEATURES Four independent adders/subtractors Two’s complement arithmetic Synchronous operation Common Clear and Clock 74F385 is designed for use with serial multipliers in implementing digital filters and butterfly networks in fast Fourier transforms PIN CONFIGURATION CP 1 F0 2 S0 3 B0 4 A0 5 A1 6 20 V CC 19 F3 18 S3 17 B3 16 A3 15 A2 14 B2 13 S2 12 F2 11 MR DESCRIPTION The 74F385 contains four independent adder/subtractor elements with common Clock and Master Reset. Each adder/subtractor contains a sum flop-flop and a carry flip-flop for synchronous operations. Flip-flop state changes occur on the rising edge of the Clock Pulse (CP) input signal. The Select (S) input should be Low for the Add (A plus B) mode and High for the Subtract (A minus B) mode. A Low signal on the asynchronous Master Reset (MR) input clears the sum flip-flop and resets the Carry flip-flop to zero in the Add mode or presets it to one in the Subtract mode. B1 7 S1 8 F1 9 GND 10 SF00928 TYPE 74F385 TYPICAL fMAX 140 MHz TYPICAL SUPPLY CURRENT (TOTAL) 55mA ORDERING INFORMATION DESCRIPTION 20-pin plastic DIP 20-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F385N N74F385D INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS A0 – A3 B0 – B3 S0 – S3 CP MR A operand inputs B operand inputs Function select inputs Clock pulse input (active rising edge) Asynchronous Master Reset input (activ...