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74F413 Dataheets PDF



Part Number 74F413
Manufacturers Fairchild
Logo Fairchild
Description 64 x 4 First-In First-Out Buffer Memory
Datasheet 74F413 Datasheet74F413 Datasheet (PDF)

www.DataSheet4U.com 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O April 1988 Revised August 1999 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description The F413 is an expandable fall-through type high-speed First-In First-Out (FIFO) buffer memory organized as 64 words by four bits. The 4-bit input and output registers record and transmit, respectively, asynchronous data in parallel form. Control pins on the input and output allow for handshakin.

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www.DataSheet4U.com 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O April 1988 Revised August 1999 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description The F413 is an expandable fall-through type high-speed First-In First-Out (FIFO) buffer memory organized as 64 words by four bits. The 4-bit input and output registers record and transmit, respectively, asynchronous data in parallel form. Control pins on the input and output allow for handshaking and expansion. The 4-bit wide, 62-bit deep fall-through stack has self-contained control logic. Features s Separate input and output clocks s Parallel input and output s Expandable without external logic s 15 MHz data rate s Supply current 160 mA max s Available in SOIC, (300 mil only) Ordering Code: Order Number 74F413PC Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Unit Loading/Fan Out Pin Names D0–D3 O0–O3 IR SI SO OR MR Description Data Inputs Data Outputs Input Ready Shift In Shift Out Output Ready Master Reset U.L. HIGH/LOW 1.0/0.667 50/13.3 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 Input IIH/IIL Output IOH/IOL 20 µA/−0.4 mA −1 mA/8 mA 20 µA/−0.4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA © 1999 Fairchild Semiconductor Corporation DS009541 www.fairchildsemi.com 74F413 Functional Description Data Input— Data is entered into the FIFO on D0–D3 inputs. To enter data the Input Ready (IR) should be HIGH, indicating that the first location is ready to accept data. Data then present at the four data inputs is entered into the first location when the Shift In (SI) is brought HIGH. An SI HIGH signal causes the IR to go LOW. Data remains at the first location until SI is brought LOW. When SI is brought LOW and the FIFO is not full, IR will go HIGH, indicating that more room is available. Simultaneously, data will propagate to the second location and continue shifting until it reaches the output stage or a full location. If the memory is full, IR will remain LOW. Data Transfer— Once data is entered into the second cell, the transfer of any full cell to the adjacent (downstream) empty cell is automatic, activated by an on-chip control. Thus data will stack up at the end of the device while empty locations will “bubble” to the front. The tPT parameter defines the time required for the first data to travel from input to the output of a previously empty device. Data Output— Data is read from the O0–O3 outputs. When data is shifted to the output stage, Output Ready (OR) goes HIGH, indicating the presence of valid data. When the OR is HIGH, data may be shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal at SO causes the OR to go LOW. Valid data is maintained while the SO is HIGH. When SO is brought LOW, the upstream data, provided that stage has valid data, is shifted to the output stage. When new valid data is shifted to the output stage, OR goes HIGH. If the FIFO is emptied, OR stays LOW, and O0–O3 remains as before, i.e., data does not change if FIFO is empty. Input Ready and Output Ready— may also be used as status signals indicating that the FIFO is completely full (Input Ready stays LOW for at least tPT) or completely empty (Output Ready stays LOW for at least tPT). Block Diagram www.fairchildsemi.com 2 74F413 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −0.5V to VCC −0.5V to +5.5V −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current −20 115 4.75 3.75 −0.4 −130 160 10% VCC 5% VCC 10% VCC 2.4 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 −1.5 Typ Max Units V V V V V µA µA µA V µA mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW .


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