Document
74F651 • 74F652 Transceivers/Registers
March 1988 Revised August 1999
74F651 • 74F652 Transceivers/Registers
General Description
These devices consist of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function.
Features
s Independent registers for A and B buses s Multiplexed real-time and stored data s Choice of non-inverting and inverting data paths 74F651 inverting 74F652 non-inverting
Ordering Code:
Order Number 74F651SC 74F651SPC 74F652SC 74F652SPC Package Number M24B N24C M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 1999 Fairchild Semiconductor Corporation
DS009581
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74F651 • 74F652
Logic Symbols
74F651 74F652
IEEE/IEC 74F651
IEEE/IEC 74F652
Unit Loading/Fan Out
Pin Names A0–A7, B0–B7 CPAB, CPBA SAB, SBA OEAB, OEBA Description A and B Inputs/ 3-STATE Outputs Clock Inputs Select Inputs Output Enable Inputs U.L. HIGH/LOW 1.0/1.0 600/106.6 (80) 1.0/1.0 1.0/1.0 1.0/1.0 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −12 mA/64 mA (48 mA) 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA
Function Table
Inputs OEAB OEBA CPAB CPBA SAB SBA L L X H L L L L H H H H H H H X L L L H H L H or L H or L H or L Inputs/Outputs (Note 1) A0 thru A7 Input Input Input Output Output Input Output B0 thru B7 Input Operating Mode Isolation Store A and B Data Not Specified Store A, Hold B Output Input Input Output Output Store A in Both Registers Hold A, Store B Store B in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus
H = HIGH Voltage Level L = LOW Voltage Level
H or L X
X X
X X X
X X X X X X X X L H H
X X X X X X L H X X H
Not Specified Input
H or L
H or L
H or L H or L
X = Immaterial = LOW-to-HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
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74F651 • 74F652
Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the Octal bus transceivers and receivers. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.
Note A: Real-Time Transfer Bus B to Bus A
Note B: Real-Time Transfer Bus A to Bus B
OEAB OEBA CPAB CPBA SAB SBA L L X X X L
OEAB OEBA CPAB CPBA SAB SBA H H X X L X
Note C: Storage
Note D: Transfer Storage Data to A or B
OEAB OEBA CPAB CPBA SAB SBA X L L H X H X X X X X X X FIGURE 1. X
OEAB OEBA CPAB CPBA SAB SBA H L H or L H or L H X
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74F651 • 74F652
Logic Diagrams
74F652
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F651
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F651 • 74F652
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V −0.5V to VCC −0.5V to +5.5V −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA
Recommende.