74F825

54F 74F825 8-Bit D-Type Flip-Flop December 1994 54F 74F825 8-Bit D-Type Flip-Flop General Description The ’F825 is an 8-bit buffered register It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems Also included in the ’F825 are multiple enables that allow multiuser control of the interface The ’F825 is functionally and pin compatible with AMD’s Am29825 Features Y Y Y Y TRI-STATE output Clock enable and clear Multiple output enables Direct replacement for AMD’s Am24825 Commercial 74F825SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C 54F825SDM (Note 2) 74F825SC (Note 1) 54F825FM (Note 2) 54F825LM (Note 2) Note 1 Devices also available in 13 reel Use suffix e SCX J24F M24B W24C E28A Note 2 Military grade device with environmental and burn-in processing Use suffix e SDMQB FMQB and LMQB Logic Symbols IEEE IEC TL F 9597 – 1 TL F 9597 – 4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9597 RRD-B30M75 Printed in U S A Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9597 – 3 TL F 9597–2 Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 150 40 (33 3) 10 10 10 10 10 10 10 ...