74HC195

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT195 4-bit parallel access shift register Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 4-bit parallel access shift register FEATURES Asynchronous master reset J, K, (D) inputs to the first stage Fully synchronous serial or parallel data transfer Shift right and parallel load capability Complement output from the last stage Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT195 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT195 performs serial, parallel, serial-to-parallel or parallel-to-serial data transfer at very high speeds. The “195” operates on two primary modes: shift right (Qo→Q1) and parallel load, which are controlled QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT195 by the state of the parallel load enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is HIGH and shifted one bit in the direction Q0 → Q1 → Q2 → Q3 following each LOW-to-HIGH clock transition. The J and K inputs provide the flexibility of the JK...