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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT299 8-bit universal shift register; 3-state
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
8-bit universal shift register; 3-state
FEATURES • Multiplexed inputs/outputs provide improved bit density • Four operating modes: – shift left – shift right – hold (store) – load data • Operates with output enable or at high-impedance OFF-state (Z) • 3-state outputs drive bus lines directly • Can be cascaded for n-bits word length • Output capability: bus driver (parallel I/Os), standard (serial outputs) • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT299 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT299
The 74HC/HCT299 contain eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the mode select inputs (S0 and S1), as shown in the mode select table. All flip-flop outputs have 3-state buffers to separate these outputs (I/O0 to I/O7) such, that they can serve as data inputs in the parallel load mode. The serial outputs (Q0 and Q7) are used for expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset input (MR) overrides the Sn and clock (CP) inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is either state, provided that the recommended set-up and hold times, relative to the rising edge of CP, are observed. A HIGH signal on the 3-state output enable inputs (OE1 or OE2) disables the 3-state buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1, when in preparation for a parallel load operation.
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay CP to Q0, Q7 CP to I/On tPHL fmax CI CI/O CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V December 1990 2 ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V MR to Q0, Q7 or I/On maximum clock frequency input capacitance input/output capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 20 20 20 50 3.5 10 120 19 19 23 46 3.5 10 125 ns ns ns MHz pF pF pF HCT UNIT
Philips Semiconductors
Product specification
8-bit universal shift register; 3-state
PIN DESCRIPTION PIN NO. 1, 19 2, 3 7, 13, 6, 14, 5, 15, 4, 16 8, 17 9 10 11 12 18 20 SYMBOL S0, S1 OE1, OE2 I/O0 to I/O7 Q0, Q7 MR GND DSR CP DSL VCC NAME AND FUNCTION mode select inputs 3-state output enable inputs (active LOW)
74HC/HCT299
parallel data inputs or 3-state parallel outputs (bus driver) serial outputs (standard output) asynchronous master reset input (active LOW) ground (0 V) serial data shift-right input clock input (LOW-to-HIGH, edge-triggered) serial data shift-left input positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
8-bit universal shift register; 3-state
74HC/HCT299
Fig.4 Functional diagram.
MODE SELECT TABLE INPUTS RESPONSE MR L H H H H Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH CP transition S1 X H L H L S0 X H H L L CP X ↑ ↑ ↑ X asynchronous reset; Q0−Q7 = LOW parallel load; I/On → Qn shift right; DSR → Q0, Q0 → Q1 etc. shift left; DSL → Q7, Q7 → Q6 etc. hold
December 1990
4
Philips Semiconductors
Product specification
8-bit universal shift register; 3-state
74HC/HCT299
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
8-bit universal shift register; 3-state
DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver (parallel I/Os) standard (serial outputs) ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC
SYMBOL PARAMETER
74HC/HCT299
TEST CONDITIONS UNIT V WAVEFORMS CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.