7-stage binary ripple counter
74HC4024
7-stage binary ripple counter
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC40...
Description
74HC4024
7-stage binary ripple counter
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024 of the 4000B series. The 74HC4024 is specified in compliance with JEDEC standard no. 7A.
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).
The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
2. Features
s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
3. Applications
s Frequency dividing circuits s Time delay circuits.
Philips Semiconductors
74HC4024
7-stage binary ripple counter
4. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol Parameter
Conditions
Min
tPHL, tPLH
fmax
CI CPD
propagation delay CP to CL = 15 pF; Q0 VCC = 5 V
-
maximum clock frequency CL = 15 pF; VCC = 5 V
-
input capacitance
-
power dissipation capacitance
VI = GND to VCC [1] ...
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