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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT75 Quad bistable transparent latch
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Quad bistable transparent latch
FEATURES • Complementary Q and Q outputs • VCC and GND on the centre pins • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT75 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
74HC/HCT75
The 74HC/HCT75 have four bistable latches. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE1-2 and LE3-4). When LEn-n is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEn-n is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEn-n will be stored in the latches. The latched outputs remain stable as long as the LEn-n is LOW.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay nD to nQ, nQ LEn-n to nQ, nQ CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC −1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. input capacitance power dissipation capacitance per latch notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 11 11 3.5 42 12 11 3.5 42 ns ns pF pF HCT UNIT
December 1990
2
Philips Semiconductors
Product specification
Quad bistable transparent latch
PIN DESCRIPTION PIN NO. 1, 14, 11, 8 2, 3, 6, 7 4 5 12 13 16, 15, 10, 9 SYMBOL 1Q to 4Q 1D to 4D LE3-4 VCC GND LE1-2 1Q to 4Q NAME AND FUNCTION complementary latch outputs data inputs latch enable input, latches 3 and 4 (active HIGH) positive supply voltage ground (0 V) latch enable input, latches 1 and 2 (active HIGH) latch outputs
74HC/HCT75
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Quad bistable transparent latch
FUNCTION TABLE OPERATING MODES data enabled data latched Notes 1. H = HIGH voltage level L = LOW voltage level q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW LEn-n transition X = don’t care H H L INPUTS LEn-n L H X nD OUTPUTS nQ L H q H L q nQ
74HC/HCT75
Fig.4 Functional diagram.
Fig.5 Logic diagram.
Dece.