74HCT112

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jun 10 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger FEATURES Asynchronous set and reset Output capability: standard ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT112 are dual negative-edge triggered JK-type flip-flops featuring individual nJ, nK, clock (nCP), set (nSD) and reset (nRD) inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT112 The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless of the levels at the other inputs. A HIGH level at the clock (nCP) input enables the nJ and nK inputs and data will be accepted. The nJ and nK inputs control the state changes of the flip-flops as shown in the function table. The nJ and nK inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Output state ch...