SN74LS76A SCHOTTKY Datasheet

SN74LS76A Datasheet, PDF, Equivalent


Part Number

SN74LS76A

Description

LOW POWER SCHOTTKY

Manufacture

ON Semiconductor

Total Page 4 Pages
Datasheet
Download SN74LS76A Datasheet


SN74LS76A
SN74LS76A
Dual JK Flip-Flop
with Set and Clear
The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and
Direct Clear inputs. These dual flip-flops are designed so that when
the clock goes HIGH, the inputs are enabled and data will be accepted.
The Logic Level of the J and K inputs will perform according to the
Truth Table as long as minimum set-up times are observed. Input data
is transferred to the outputs on the HIGH-to-LOW clock transitions.
MODE SELECT – TRUTH TABLE
OPERATING
INPUTS
OUTPUTS
MODE
SD CD
J
K
Q
Q
Set L H X X H L
Reset (Clear)
HLXXLH
*Undetermined
L L XXHH
Toggle
HHh h q q
Load “0” (Reset) H H l h L H
Load “1” (Set)
HHh l HL
Hold
HH
l
l qq
* Both outputs will be HIGH while both SD and CD are LOW, but the output
states are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Immaterial
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) = (or output) one setup time prior to the HIGH–to–LOW clock transition
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
ORDERING INFORMATION
Device
Package
Shipping
SN74LS76AN 16 Pin DIP 2000 Units/Box
SN74LS76AD
16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS76A/D

SN74LS76A
SN74LS76A
LOGIC DIAGRAM
LOGIC SYMBOL
27
Q Q 16 K SD Q 15 12 K SD Q 11
1 CP
6 CP
CLEAR (CD)
4
SET (SD)
J CD Q 14 9
J K3
VCC = PIN 5
GND = PIN 13
CLOCK (CP)
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
J CD Q
8
10
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
IIH Input HIGH Current
J, K
Clear
Clock
J, K
Clear
Clock
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
20
60 µA VCC = MAX, VIN = 2.7 V
80
0.1
0.3 mA VCC = MAX, VIN = 7.0 V
0.4
IIL Input LOW Current
J, K
Clear, Clock
– 0.4
– 0.8
mA
VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1)
– 20 –100 mA
ICC Power Supply Current
6.0 mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
VCC = MAX
VCC = MAX
Symbol
Parameter
Min Typ Max Unit
Test Conditions
fMAX
tPLH
tPHL
Maximum Clock Frequency
Clock, Clear, Set to Output
30 45
MHz
15 20
ns
15 20
ns
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
tW Clock Pulse Width High
tW Clear Set Pulse Width
ts Setup Time
th Hold Time
20 ns
25 ns
VCC = 5.0 V
20 ns
0 ns
http://onsemi.com
2


Features SN74LS76A Dual JK Flip-Flop with Set and Clear The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direc t Clear inputs. These dual flip-flops a re designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of th e J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data i s transferred to the outputs on the HIG H-to-LOW clock transitions. http://onse mi.com LOW POWER SCHOTTKY MODE SELECT – TRUTH TABLE OPERATING MODE Set Res et (Clear) *Undetermined Toggle Load 0” (Reset) Load “1” (Set) Hold * INPUTS SD L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l OUTP UTS Q H L H q L H q Q L H H q H L q 16 1 Both outputs will be HIGH while bot h SD and CD are LOW, but the output sta tes are unpredictable if SD and CD go H IGH simultaneously. PLASTIC N SUFFIX C ASE 648 H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Immaterial l, h (q) = Lower case letters indicat.
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