MT4C16270

TECHNOLOGY, INC. MT4C16270 256K x 16 DRAM DRAM FEATURES Industry-standard x16 pinouts, timing, functions and packages High-performance CMOS silicon-gate process Single +5V ±10% power supply* Low power, 3mW standby; 300mW active, typical All device pins are TTL-compatible 512-cycle refresh in 8ms (9 row- and 9 column addresses) Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN Extended Data-Out (EDO) PAGE MODE access cycle BYTE WRITE and BYTE READ access cycles 256K x 16 DRAM 5V, EDO PAGE MODE PIN ASSIGNMENT (Top View) 40-Pin SOJ (DA-6) OPTIONS Timing 40ns access 50ns access 60ns access Packages Plastic SOJ (400 mil) MARKING -4* -5* -6 DJ Part Number Example: MT4C16270DJ-4 *40ns and 50ns access specifications are limited to a VCC range of ±5%. Contact factory for availability. KEY TIMING PARAMETERS SPEED -4 -5 -6 tRC tRAC tPC tAA tCAC tCAS tCP 75ns 100ns 110ns 40ns 50ns 60ns 15ns 20ns 25ns 20ns 25ns 30ns 12ns 15ns 15ns 6ns 8ns 10ns 6ns 8ns 10ns Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC NC WE# RAS# NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vss DQ16 DQ15 DQ14 DQ13 Vss DQ12 DQ11 DQ10 DQ9 NC CASL# CASH# OE# A8 A7 A6 A5 A4 Vss GENERAL DESCRIPTION The MT4C16270 is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x16 configuration. The MT4C16270 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins. T...