B/W Cameras. ICX099AL Datasheet

ICX099AL Cameras. Datasheet pdf. Equivalent

ICX099AL Datasheet
Recommendation ICX099AL Datasheet
Part ICX099AL
Description 1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras
Feature ICX099AL; ICX099AL 1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras For the avail.
Manufacture Sony
Datasheet
Download ICX099AL Datasheet





Sony ICX099AL
ICX099AL
1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras
For the availability of this product, please contact the sales office.
Description
The ICX099AL is a 1/2-inch optical interline CCD
solid-state image sensor with a square pixel array
and 800K effective pixels. Progressive scan allows all
pixels' signals to be output independently within
approximately 1/15 second. Also, the adoption of
high-speed mode supports 30 frames per second.
This chip features an electronic shutter with variable
charge-storage time which makes it possible to
realize high resolution, full-frame still image without a
mechanical shutter. Further, high sensitivity and low
dark current are achieved through the adoption of
HAD (Hole-Accumulation Diode) sensors.
This chip is suitable for applications such as high
resolution cameras for FA, etc.
Features
Progressive scan allows individual readout of the
image signals from all pixels.
High horizontal and vertical resolution still image
without a mechanical shutter.
Supports 30 frames per second mode
Square pixel
Horizontal drive frequency: 14.31818MHz
No voltage adjustments (reset gate and substrate
bias are not adjusted.)
High resolution, high sensitivity, low dark current
Continuous variable-speed shutter
Low smear
Excellent antiblooming characteristics
20 pin DIP (Cer-DIP)
Pin 1
2
V
3
Pin 11
H
7
40
Optical black position
(Top View)
Device Structure
Interline CCD image sensor
Optical size:
1/2-inch format
Number of effective pixels: 1034 (H) × 779 (V) approx. 800K pixels
Total number of pixels:
1077 (H) × 788 (V) approx. 850K pixels
Chip size:
7.60mm (H) × 6.20mm (V)
Unit cell size:
6.25µm (H) × 6.25µm (V)
Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 7 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 29
Vertical 1
Substrate material:
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97747-PS



Sony ICX099AL
Block Diagram and Pin Configuration
(Top View)
10 9 8 7 6 5 4 3 2 1
ICX099AL
Horizontal register
Note)
Note)
: Photo sensor
Pin Description
11 12 13 14 15 16 17 18 19 20
Pin No. Symbol
Description
Pin No. Symbol
Description
1 Vφ1
Vertical register transfer clock
11 VDD
Supply voltage
2 Vφ2A Vertical register transfer clock
12 GND GND
3 NC
4 Vφ2B Vertical register transfer clock
13 φSUB Substrate clock
14 CSUB Substrate bias1
5 NC
15 NC
6 Vφ3
Vertical register transfer clock
16 NC
7 GND GND
17 VL
Protective transistor bias
8 GND GND
18 φRG Reset gate clock
9 NC
19 Hφ1
Horizontal register transfer clock
10 VOUT Signal output
20 Hφ2
Horizontal register transfer clock
1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
Absolute Maximum Ratings
Item
VDD, VOUT, φRG – φSUB
Vφ2A, Vφ2B φSUB
Against φSUB Vφ1, Vφ3, VL φSUB
Hφ1, Hφ2, GND – φSUB
CSUB φSUB
VDD, VOUT, φRG, CSUB – GND
Against GND Vφ1, Vφ2A, Vφ2B, Vφ3 – GND
Hφ1, Hφ2 – GND
Against VL
Vφ2A, Vφ2B – VL
Vφ1, Vφ3, Hφ1, Hφ2, GND – VL
Between input
clock pins
Voltage difference between vertical clock input pins
Hφ1 – Hφ2
Hφ1, Hφ2 – Vφ3
Storage temperature
Operating temperature
2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
Ratings
–40 to +10
–50 to +15
–50 to +0.3
–40 to +0.3
–25 to
–0.3 to +18
–10 to +18
–10 to +5
–0.3 to +28
–0.3 to +15
to +15
–5 to +5
–13 to +13
–30 to +80
–10 to +60
Unit Remarks
V
V
V
V
V
V
V
V
V
V
V 2
V
V
°C
°C



Sony ICX099AL
ICX099AL
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Symbol Min.
VDD 14.55
VL
φSUB
φRG
Typ.
15.0
1
2
2
Max. Unit
15.45 V
Remarks
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min.
IDD
Typ.
6.0
Max. Unit
mA
Remarks
Clock Voltage Conditions
Item Symbol
Readout clock voltage VVT
VVH02A
VVH1, VVH2A,
VVH2B, VVH3
VVL1, VVL2A,
VVL2B, VVL3
Vertical transfer clock
voltage
Vφ1, Vφ2A,
Vφ2B, Vφ3
| VVL1 – VVL3 |
VVHH
VVHL
VVLH
VVLL
Horizontal transfer
clock voltage
VφH
VHL
Reset gate clock
voltage
VφRG
VRGLH – VRGLL
VRGL – VRGLm
Substrate clock voltage VφSUB
Min. Typ. Max. Unit
14.55 15.0 15.45 V
–0.05 0 0.05 V
Waveform
diagram
1
2
Remarks
VVH = VVH02A
–0.2 0 0.05 V
2
–5.8 –5.5 –5.2 V
2 VVL = (VVL1+VVL3)/2
5.2 5.5 5.8 V
0.1
0.3
1.0
0.5
0.5
4.75 5.0 5.25
–0.05 0 0.05
3.0 3.3 5.5
0.4
0.5
19.75 20.5 21.25
V
V
V
V
V
V
V
V
V
V
V
2
2
2 High-level coupling
2 High-level coupling
2 Low-level coupling
2 Low-level coupling
3
3
4
4 Low-level coupling
4 Low-level coupling
5
–3–





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