Microprocessor. LR4102 Datasheet

LR4102 Microprocessor. Datasheet pdf. Equivalent

LR4102 Datasheet
Recommendation LR4102 Datasheet
Part LR4102
Description Microprocessor
Feature LR4102; TinyRISC® LR4102 Microprocessor Datasheet The TinyRISC LR4102 Microprocessor is a compact, high perf.
Manufacture LSI Logic Corporation
Download LR4102 Datasheet

LSI Logic Corporation LR4102
TinyRISC® LR4102
The TinyRISC LR4102 Microprocessor is a compact, high performance
32-bit microprocessor implemented in the LSI Logic G11™ technology.
The LR4102 is a complete microprocessor solution with caches, an
external bus interface with built-in memory controllers, and on-chip
debug. The LR4102 is built using the EZ4102 EasyMACRO subsystem,
available to customers through the LSI Logic CoreWare® program.
The LR4102 provides a 32-bit FBusMACRO to control all off-chip data
transactions (including DRAM or SDRAM) and an EJTAG interface for
on-chip debug with PC trace output. Figure 1 illustrates the LR4102 chip.
Figure 1 LR4102 Block Diagram
32-bit TinyRISC
4102 CPU
and FastMDU
BIU and Cache
Controller (BBCC)
Two 32-bit Timers
SerialICE™-1 Port
Extended Debug MACRO
PC Trace
The LR4102 microprocessor is powered by either 2.5 V (for 85 MHz
operation) or 1.8 V (for 50 MHz operation). The chip I/O ring requires
3.3 V. With a system clock of 85 MHz, peak performance is 85 MIPS and
sustained performance is estimated at 68 MIPS. With a 50 MHz clock,
performance is 50 MIPS peak and 40 MIPS sustained.
March 2000
Copyright © 1998–2000 by LSI Logic Corporation. All rights reserved.

LSI Logic Corporation LR4102
LR4102 Features
R3000 MIPS CPU executes
– 16 Kbytes of two-way
set-associative I-Cache
32-bit FBus, a fast
demultiplexed multimaster
bus, with built in control of:
– 8 Kbytes of direct-mapped
Clock module with integrated
PLL and programmable clock
– RAM, EPROM, or similar speeds
simple devices
– General-purpose I/O
LSI Logic G11 Technology
Two 32-bit Timers
– 4/5 cycle multiply and
accumulate (32-bit to
– 34/35 cycle divide
BBCC with four writeback
buffers included
– 0.18 µ Leff (0.25 µ drawn)
– 2.5 or 1.8 V operation
Performance and Compatibility
Clock speed is 85 MHz at 2.5 V
(85 MIPS peak and estimated
68 MIPS sustained)
Low power mode allows LR4102
to use minimal power when idle
MMU with 64-entry TLB RAM Compatible with the full range of
MIPS and third-party software
EJTAG Version 2.0.0:
development tools
– Nonintrusive debug
– Real-time PC trace
– Hardware breakpoints
16-bit and 32-bit code can be
mixed arbitrarily with full support
on a subroutine basis
SerialICE-1 Port included for All instructions execute in one
backward compatibility with
cycle except for Load and Store,
other TinyRISC designs
Move To Coprocessor, and Move
JTAG Boundary Scan
On-Chip Memory (OCM),
1 Kbyte
From Coprocessor, which
execute in two cycles, and MDU
instructions, which execute in
several cycles
2 TinyRISC LR4102 Microprocessor

LSI Logic Corporation LR4102
Block Diagram
This section provides short descriptions of the major components of the
LR4102, as shown in Figure 1.
The CPU performs all arithmetic, logical, shift, and address calculations.
The CPU supports EJTAG debug and is closely coupled with the
FastMDU. The FastMDU calculates all multiply and divide operations for
the LR4102, and provides 4/5 cycle multiply and accumulate operations
(32 bit to 64 bit), 34/35 cycle divide, saturated math, and overflow
The memory management unit (MMU) translates virtual addresses from
the CPU into physical addresses and includes a 64-entry translation
look-aside buffer (TLB) RAM.
The BIU and cache controller (BBCC) provides an internal bus interface
and connects the CPU to the caches. For the caches, the LR4102
contains 16 Kbytes of two-way set-associative I-Cache and 8 Kbytes of
direct-mapped D-Cache. Four Write Buffers are integrated with the
BBCC in the LR4102 design.
The 32-bit FBusMACRO (FBM) controls the FBus, a dedicated,
multimaster bus that connects off-chip logic with the LR4102. The FBus
allows seamless LR4102 connection to a variety of devices, including
EPROM, FLASH, RAM, DRAM, SDRAM, and general-purpose I/O pins.
The FBus also supports burst read (one cycle) and write, built-in
arbitration for an external FBus master, and snooping of external write
accesses to memory. Internally, the FBusMACRO interfaces mainly with
the BBCC module.
Each 32-bit Timer can count down from a preloaded value, roll over or
stop at zero, generate an interrupt on zero, or act as bus watchdog. The
CPU can program either of the two internal 32-bit timers.
The LR4102 includes 1 Kbyte of on-chip memory (OCM).
The Clock Controller steps CPU clock speed up or down, and can stop
the internal LR4102 clock altogether. The LR4102 also supports a low
power mode. The LR4102 Clock Controller is designed to support a
crystal or canned oscillator, and has an on-chip PLL for frequency
TinyRISC LR4102 Microprocessor

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