I/O Processor. 80321 Datasheet

80321 Processor. Datasheet pdf. Equivalent

80321 Datasheet
Recommendation 80321 Datasheet
Part 80321
Description I/O Processor
Feature 80321; Intel® 80321 I/O Processor Datasheet Product Features s s s s Core Features — Integrated Intel®.
Manufacture Intel
Datasheet
Download 80321 Datasheet





Intel 80321
Intel® 80321 I/O Processor
Datasheet
Product Features
s Core Features
s DMA Controller
— Integrated Intel® XScaleCore
— Two Independent Channels Connected
— ARM* V5T Instruction Set
— ARM V5E DSP Extensions
— 400 MHz and 600 MHz
— Write Buffer, Write-back Cache
to Internal Bus
— Up to 1064 MB/s Burst Support in
PCI-X Mode
— Up to 1600 MB/s Burst Support for
Internal Bus
s PCI Bus Interface
— Two 1-KB Queues in Ch-0 and Ch-1
PCI Local Bus Specification, Rev. 2.2
compliant
— 232 Addressing Range on Internal Bus
Interface
PCI-X Addendum to the PCI Local Bus
— 264 Addressing Range on PCI Interface
Specification, Rev. 1.0a
s Application Accelerator Unit
— 64-bit/66MHz Operation in PCI Mode
— Performs XOR on Read Data
—64-bit/133MHz Operation in PCI-X Mode — Compute Parity Across Local Memory
— Support 32-bit PCI Initiators and Targets
Blocks
— Four Split Read Requests as Initiator
— Eight Split Read Requests as Target
— 64-bit Addressing Support
— 1 KB/512-byte Store Queue
s I2C Bus Interface Units
— Two Separate I2C Units
s Memory Controller
— Serial Bus
—PC200 Double Data Rate (DDR) SDRAM — Master/Slave Capabilities
— Up to 1 GB of 64-bit DDR SDRAM
— System Management Functions
— Up to 512 MB of 32-bit DDR SDRAM s SSP Serial Port
— Single-bit Error Correction, Multi-bit
Support (ECC)
— Full-duplex Synchronous Serial Interface
— Supports 7.2 KHz to 1.84 MHz Bit Rates
— 1024-byte Posted Memory Write Queue s Peripheral Performance Monitoring Unit
— 40- and 72-bit wide Memory Interface
— One Dedicated Global Time Stamp
Counter
s Address Translation Unit
— Fourteen Programmable Event Counters
— 2 KB or 4 KB Outbound Read Queue
— Three Control/Status Registers
— 4 KB Outbound Write Queue
s Timers
— 4 KB Inbound Read and Write Queue
— Two Dual-programmable 32-bit Timers
—Connects Internal Bus to PCI/PCI-X Bus — Watchdog Timer
s 544-Ball, Plastic Ball Grid Array (PBGA)
s Eight General Purpose I/O Pins
Document Number: 273518-002
June 2002



Intel 80321
Intel® 80321 I/O Processor
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel® Intel® 80321 I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Intel® internal code names are subject to change.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright© Intel Corporation, 2002
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*Other names and brands may be claimed as the property of others.
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June 2002
Datasheet



Intel 80321
Intel® 80321 I/O Processor
Contents
1.0 Introduction......................................................................................................................... 7
1.1 About This Document............................................................................................7
1.1.1 Terminology..............................................................................................7
1.1.2 Other Relevant Documents ...................................................................... 8
1.2 About the Intel® 80321 I/O Processor ................................................................... 9
2.0 Features ...........................................................................................................................11
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Internal Bus ......................................................................................................... 11
DMA Controller.................................................................................................... 11
Address Translation Unit .....................................................................................12
Messaging Unit.................................................................................................... 12
Memory Controller............................................................................................... 12
Peripheral Bus Interface...................................................................................... 12
Application Accelerator Unit ................................................................................ 13
Performance Monitoring Unit............................................................................... 13
I2C Bus Interface Units ........................................................................................ 13
Synchronous Serial Port Unit ..............................................................................13
3.0 Package Information ........................................................................................................14
3.1 Package Introduction........................................................................................... 14
3.1.1 Functional Signal Definitions ..................................................................14
3.1.2 544-Lead PBGA Package ...................................................................... 25
3.2 Package Thermal Specifications .........................................................................39
3.2.1 Thermal Specifications ........................................................................... 39
3.2.1.1 Ambient Temperature................................................................ 39
3.2.1.2 Case Temperature .................................................................... 39
3.2.1.3 Thermal Resistance ..................................................................39
3.2.2 Thermal Analysis .................................................................................... 40
3.3 Socket Information .............................................................................................. 41
3.3.1 Socket-Header Vendor........................................................................... 41
3.3.2 Burn-in Socket Vendor ........................................................................... 41
3.3.3 Shipping Tray Vendor............................................................................. 41
3.3.4 Logic Analyzer Interposer Vendor .......................................................... 41
3.3.5 JTAG Emulator Vendor .......................................................................... 42
4.0 Electrical Specifications.................................................................................................... 43
4.1 Absolute Maximum Ratings................................................................................. 43
4.2 VCCPLL Pin Requirements ................................................................................... 43
4.3 Targeted DC Specifications................................................................................. 44
4.4 Targeted AC Specifications................................................................................. 46
4.4.1 Clock Signal Timings ..............................................................................46
4.4.2 PCI Interface Signal Timings ..................................................................47
4.4.3 DDR SDRAM Interface Signal Timings .................................................. 48
4.4.4 Peripheral Bus Interface Signal Timings ................................................ 48
4.4.5 I2C Interface Signal Timings................................................................... 48
4.4.6 SSP Interface Signal Timings................................................................. 49
4.4.7 Boundary Scan Test Signal Timings ...................................................... 50
4.5 AC Timing Waveforms ........................................................................................ 51
4.6 AC Test Conditions ............................................................................................. 55
Datasheet
June 2002
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