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ST70235A Dataheets PDF



Part Number ST70235A
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description ASCOTTM DMT TRANSCEIVER
Datasheet ST70235A DatasheetST70235A Datasheet (PDF)

ST70235A ASCOTTM DMT TRANSCEIVER PRELIMINARY DATA s DMT MODEM FOR CPE ADSL, COMPATIBLE WITH THE FOLLOWING STANDARDS: - ANSI T1.413 ISSUE 2 - ITU-T G.992.1 (G.DMT) - ITU-T G.992.2 (G.LITE) 1 & 2) OR BITSTREAM INTERFACE s SUPPORTS EITHER ATM (UTOPIA LEVEL s 16 BIT MULTIPLEXED MICROPROCESSOR INTERFACE (LITTLE AND BIG ENDIAN COMPATIBILITY) s ANALOG FRONT END MANAGEMENT s DUAL LATENCY INTERLEAVED PATHS: FAST AND s ATM’S PHY LAYER: CELL PROCESSING (CELL DELINEATION, CELL INSERTION, HEC) s ADSL’S.

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ST70235A ASCOTTM DMT TRANSCEIVER PRELIMINARY DATA s DMT MODEM FOR CPE ADSL, COMPATIBLE WITH THE FOLLOWING STANDARDS: - ANSI T1.413 ISSUE 2 - ITU-T G.992.1 (G.DMT) - ITU-T G.992.2 (G.LITE) 1 & 2) OR BITSTREAM INTERFACE s SUPPORTS EITHER ATM (UTOPIA LEVEL s 16 BIT MULTIPLEXED MICROPROCESSOR INTERFACE (LITTLE AND BIG ENDIAN COMPATIBILITY) s ANALOG FRONT END MANAGEMENT s DUAL LATENCY INTERLEAVED PATHS: FAST AND s ATM’S PHY LAYER: CELL PROCESSING (CELL DELINEATION, CELL INSERTION, HEC) s ADSL’S OVERHEAD MANAGEMENT s REED SOLOMON ENCODE/DECODE s TRELLIS ENCODE/DECODE (VITERBI) s DMT MAPPING / DEMAPPING OVER 256 CARRIERS GENERAL DESCRIPTION The ST70235A is the DMT modem and ATM framer of the STMicroelectronics ASCOT™ chipset. When coupled with ST70134 analog front-end and an external controller running dedicated firmware, the product fulfills ANSI T1.413 "Issue 2" DMT ADSL specification. The chip supports UTOPIA level 1 and UTOPIA level 2 interface. The ST70235A can be split up into two different sections. The physical one performs the DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving and 4D trellis coding. The ATM section embodies framing functions for the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed Solomon error corrections, with and without interleaving. The ST70235A is controlled and programmed by an external controller (ADSL Transceiver Controller, ATC) that sets the programmable coefficients. The firmware controls the initialization phase and carries out the consequent adaptation operations. s FINE (2PPM) TIMING RECOVER USING ROTOR AND ADAPTATIVE FREQUENCY DOMAIN EQUALIZING s TIME DOMAIN EQUALIZATION s FRONT END DIGITAL FILTERS s 0.25µm HCMOS7 TECHNOLOGY s 144 PIN TQFP s POWER CONSUMPTION: 0.4 WATT APPLICATIONS Routers at SOHO, stand-alone modems, PC modems. TQFP144 Full Plastic (20 x 20 x 1.40 mm) ORDER CODE: ST70235A October 2001 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/28 ST70235A Figure 1 : Block Diagram TEST SIGNALS CLOCK TEST MODULE DATA SYMBOL TIMING UNIT VCXO AFE INTERFACE DSP FRONT-END FFT/IFFT ROTOR TRELLIS CODING MAPPER/ DEMAPPER GENERIC TC REED/ SOLOMON INTERFACE MODULE UTOPIA AFE CONTROL AFE CONTROL INTERFACE CONTROLLER INTERFACE ATM SPECIFIC TC CONTROLLER BUS GENERAL PURPOSE I/Os Transient Energy Capabilities ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM) and for the Charged Device Model (CDM). The pins of the device are to be able to withstand minimum 2000V for the HBM and minimum 250V for CDM. Latch-up The maximum sink or source current from any pin is limited to 200mA to prevent latch-up. ABSOLUTE MAXIMUM RATINGS Symbol VDD 3.3 VDD 1.8 Ptot Tamb Rth J/A I3.3 I1.8 Parameter Supply Voltage Supply Voltage Total Power Dissipation Ambient Temperature 1m/s airflow Thermal Resistivity Current Consumption Current Consumption 0 38 14 135 Min. 3.0 1.62 Typ. 3.3 1.8 300 Max. 3.6 1.98 400 70 Unit V V mW °C °C/W mA mA 2/28 ST70235A Figure 2 : Pin Connection DISABLE_COMP COMP_VDD_1.8 COMP_ROUT RESERVED RESERVED RESERVED CTRLDATA AFRXD_3 AFRXD_2 AFRXD_1 AFRXD_0 AFTXD_3 AFTXD_2 AFTXD_1 AFTXD_0 GP_OUT TESTSE PDOWN VDD 3.3 VDD 3.3 VDD 3.3 VDD 1.8 VDD 3.3 TRSTB CLWD MCLK IDDq TMS TDO VSS VSS VSS VSS 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VSS AD_0 AD_1 AD_2 VDD 3.3 AD_3 AD_4 VSS AD_5 AD_6 VDD 3.3 AD_7 AD_8 AD_9 VSS AD_10 AD_11 VDD 1.8 AD_12 VSS PCLK VDD 3.3 AD_13 AD_14 AD_15 VSS BE1 ALE VDD 3.3 CSB WR_RDB RDYB OBC_TYPE INTB RESETB VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VSS TCK TDI 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 VDD 1.8 RESERVED RESERVED RESERVED RESERVED RESERVED VSS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED VDD 3.3 RESERVED RESERVED RESERVED VSS RESERVED U_TX_ADDR_0 U_TX_ADDR_1 U_TX_ADDR_2 VDD 1.8 U_TX_ADDR_3 U_TX_ADDR_4 U_TX_DATA_0 U_TX_DATA_1 VDD 1.8 U_TX_DATA_2 U_TX_DATA_3 U_TX_DATA_4 U_TX_DATA_5 VDD 3.3 U_TX_DATA_6 U_TX_DATA_7 VSS ST70235A 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD 1.8 VSS VDD 3.3 VSS VDD 3.3 GP_IN0 VSS VDD 3.3 U_RXDATA_2 U_RXDATA_3 U_RXDATA_4 U_RXDATA_5 U_RXDATA_6 U_RXDATA_7 U_RX_ADDR_0 U_RX_ADDR_1 U_RX_ADDR_2 U_RX_ADDR_3 U_RX_ADDR_4 VDD 1.8 U_RXENBB U_RXDATA_0 U_RXDATA_1 U_RXCLAV U_RX_REFB U_TX_REFB U_TX_CLAV U_TXENBB U_RXSOC U_TXSOC U_RXCLK U_TXCLK VDD 3.3 GP_IN1 VSS VSS 3/28 ST70235A PIN FUNCTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 4/28 VSS AD_0 AD_1 AD_2 VDD 3.3 AD_3 A.


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