Document
BB305M
Build in Biasing Circuit MOS FET IC UHF/VHF RF Amplifier
ADE-208-607C (Z) 4th. Edition May 1998 Features
• • • • Build in Biasing Circuit; To reduce using parts cost & PC board space. Superior cross modulation characteristics. High gain; (PG = 28 dB typ. at f = 200 MHz) Wide supply voltage range; Applicable with 5V to 9V supply voltage. • Withstanding to ESD; Build in ESD absorbing diode. Withstand up to 200V at C=200pF, Rs=0 conditions. • Provide mini mold packages; MPAK-4(SOT-143mod)
Outline
MPAK-4
2 3 1 4
1. Source 2. Gate1 3. Gate2 4. Drain
Note: 1. Marking is “EW–”. 2. BB305M is individual type number of HITACHI BBFET.
BB305M
Absolute Maximum Ratings (Ta = 25°C)
Item Drain to source voltage Gate1 to source voltage Symbol VDS VG1S VG2S ID Pch Tch Tstg Ratings 12 +10 –0 Gate2 to source voltage Drain current Channel power dissipation Channel temperature Storage temperature ±10 25 150 150 –55 to +150 V mA mW °C °C Unit V V
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BB305M
Electrical Characteristics (Ta = 25°C)
Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Symbol Min V(BR)DSS V(BR)G1SS V(BR)G2SS 12 +10 ±10 — — 0.4 0.4 2.3 1.1 — 10 — 23 — 24 — — — Typ — — — — — — — 2.8 1.5 Max — — — +100 ±100 1.0 1.0 3.5 1.9 Unit V V V nA nA V V pF pF pF mA mA mS mS dB dB dB dB Test Conditions I D = 200µA, VG1S = VG2S = 0 I G1 = +10 µA, VG2S = VDS = 0 I G2 = ±10µA, VG1S = VDS = 0 VG1S = +9V, V G2S = VDS = 0 VG2S = ±9V, VG1S = VDS = 0 VDS = 5V, VG2S = 4V, ID = 100µA VDS = 5V, VG1S = 5V, ID = 100µA VDS = 5V, VG1 = 5V VG2S =4V, RG = 82kΩ f = 1MHz VDS = 5V, VG1 = 5V, VG2S = 4V RG = 82kΩ VDS = 9V, VG1 = 9V, VG2S =6V RG = 220kΩ VDS = 5V, VG1 = 5V, VG2S =4V RG =82kΩ, f = 1kHz VDS = 9V, VG1 = 9V, VG2S =6V RG = 220kΩ, f = 1kHz VDS = 5V, VG1 = 5V, VG2S =4V RG = 82kΩ, f = 200MHz VDS = 9V, VG1 = 9V, VG2S =6V RG = 220kΩ, f = 200MHz VDS = 5V, VG1 = 5V, VG2S =4V RG = 82kΩ, f = 200MHz VDS = 9V, VG1 = 9V, VG2S =6V RG = 220kΩ, f = 200MHz
Gate1 to source cutoff current I G1SS Gate2 to source cutoff current I G2SS Gate1 to source cutoff voltage VG1S(off) Gate2 to source cutoff voltage VG2S(off) Input capacitance Output capacitance c iss c oss
Reverse transfer capacitance c rss Drain current I D(op) 1 I D(op) 2 Forward transfer admittance |yfs|1 |yfs|2 Power gain PG1 PG2 Noise figure NF1 NF2
0.017 0.04 15 13 28 28 28 28 1.4 1.4 20 — — — — — 1.9 —
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BB305M
Main Characteristics
Test Circuit for Operating Items (I , |yfs|, Ciss, Coss, Crss, NF, PG) D(op)
VG2 Gate 2 Gate 1
RG
VG1
A ID
Drain
Source
Power Gain, Noise Figure Test Circuit
VT 1000p
VG2 1000p
VT 1000p
47k Input(50 ¶) L1 1000p 36p
1000p
47k
BBFET L2 1000p
47k Output(50 ¶) 10p max
1000p 1SV70 RG 82k
RFC
1SV70
1000p V D = VG1 Unit @Resistance @( ¶) @ @ Capacitance @(F)
L1 : 1mm Enameled Copper Wire,Inside dia 10mm, 2Turns L2 : 1mm Enameled Copper Wire,Inside dia 10mm, 2Turns RFC : 1mm Enameled Copper Wire,Inside dia 5mm, 2Turns
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BB305M
Maximum Channel Power Dissipa.